ISL6141 Datasheet, PDF (17/19 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6141, ISL6151
The brick’s output capacitance is also determined by the
system, including load regulation considerations. However, it
can affect the ISL6141/51, depending upon how it is
enabled. For example, if the PWRGD signal is not used to
enable the brick, the following could occur. Sometime during
the inrush current time, as the main power supply starts
charging the brick input capacitors, the brick itself will start
working, and start charging its output capacitors and load;
that current has to be added to the inrush current. In some
cases, the sum could exceed the Over-Current shutdown,
which would shut down the whole system! Therefore,
whenever practical, it is advantageous to use the PWRGD
output to keep the brick off at least until the input caps are
charged up, and then start-up the brick to charge its output
caps.
Typical brick regulators include models such as Lucent
JW050A1-E or Vicor VI-J30-CY. These are nominal -48V
input, and 5V outputs, with some isolation between the input
and output.
Applications: Optional Components
In addition to the typical application, and the variations
already mentioned, there are a few other possible
components that might be used in specific cases. See Figure
34 for some possibilities.
If the input power supply exceeds the 100V absolute
maximum rating, even for a short transient, that could cause
permanent damage to the IC, as well as other components
on the board. If this cannot be guaranteed, a voltage
suppressor (such as the SMAT70A, D1) is recommended.
When placed from V_DD to V_EE on the board, it will clamp the
voltage.
If transients on the input power supply occur when the
supply is near either the OV or UV trip points, the GATE
could turn on or off momentarily. One possible solution is to
add a filter cap C4 to the V_DD pin, through isolation resistor
R10. A large value of R10 is better for the filtering, but be
aware of the voltage drop across it. For example, a 1kΩ
resistor, with 2.4mA of I_DD would have 2.4V across it and
dissipate 2.4mW. Since the UV and OV comparators are
referenced with respect to the V_EE supply, they should not
be affected. But the GATE clamp voltage could be offset by
the voltage across the extra resistor.
The switch SW1 is shown as a simple push button. It can be
replaced by an active switch, such as an NPN or NFET; the
principle is the same; pull the UV node below its trip point,
and then release it (toggle low). To connect an NFET, for
example, the DRAIN goes to UV; the source to V_EE, and the
GATE is the input; if it goes high (relative to V_EE), it turns the
NFET on, and UV is pulled low. Just make sure the NFET
resistance is low compared to the resistor divider, so that it
has no problem pulling down against it.
R8 is a pull-up resistor for PWRGD, if there is no other
component acting as a pull-up device. The value of R8 is
determined by how much current is needed when the pin is
pulled low (also affected by the V_DD voltage); and it should
be pulled low enough for a good logic low level. An LED can
also be placed in series with R8, if desired. In that case, the
criteria is the LED brightness versus current.
GND
GND
R4
R10*
R8*
(SHORT PIN)
G
SW1*
NFET*
(INSTEAD
OF SW1)
C4*
D1*
V_DD
UV
R5
OV _VEE
ISL6141 (L)
SENSE
GATE
PWRGD
DRAIN
R6
GND
CL*
R3
C1
R2 ^C2
-V IN
R1
Q1
-V OUT
FIGURE 34. ISL6141/51 OPTIONAL COMPONENTS (SHOWN WITH *)
17