ISL6141 Datasheet, PDF (15/19 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6141, ISL6151
meet the requirement, and are also readily available standard
values.
The three resistor divider (R4, R5, R6) is the recommended
approach for most cases. But if acceptable values can’t be
found, then consider 2 separate resistor dividers (one for
each pin, both from V_DD to V_EE). This also allows the user to
adjust or trim either trip point independently. Some
applications employ a short pin ground on the connector tied
to R4 to ensure the hot plug device is fully powered up
before the UV and OV pins (tied to the short pin ground) are
biased. This ensures proper control of the GATE is
maintained during power up. This is not a requirement for the
ISL6141/51 however the circuit will perform properly if a
short pin scheme is implemented (reference Figure 34).
Supply ramping
As previously mentioned the UV and OV pins can be used to
detect under and Over-Voltage conditions on the input
supply. Figures 28 and 29 illustrate the GATE shutdown
response and the UV/OV hysteresis as a typical power
supply is ramped from 0 to 80V, and then from 80V to 0V.
FIGURE 28. SUPPLY RAMP-UP
As the supply ramps up, the UV threshold is reached at
43.6V and the FET begins to turn on. Within 40ms the GATE
is fully on and the device is operating normally. As the supply
continues to ramp up the Over-Voltage threshold is
exceeded at approximately 70.5V and the GATE is quickly
shut down as expected. In figure 29 the GATE voltage
begins in the off state as the supply voltage is above the OV
set point. As the supply voltage decreases the GATE turns
on at about 69V (roughly a 1.5 volt hysteresis). Some 800ms
later (a characteristic of the supply used) the UV high to low
threshold is met at approximately 38.5 volts (about 5.0V of
hysteresis) and the GATE is shut off.
FIGURE 29. SUPPLY RAMP-DOWN
Applications: PWRGD/PWRGD
The PWRGD/PWRGD outputs are typically used to directly
enable a power module, such as a DC/DC converter. The
PWRGD (ISL6141) is used for modules with active low
enable (L version), and PWRGD (ISL6151) for those with
active high enable (H version). The modules usually have a
pull-up device built-in, as well as an internal clamp. If not, an
external pull-up resistor may be needed. If the pin is not
used, it can be left open.
For both versions at initial start-up, when the DRAIN to V_EE
voltage differential is less than 1.3V and the GATE voltage is
within 2.5V (V_GH) of its normal operating voltage (13.6V),
power is considered good and the PWRGD/PWRGD pins
will go active. At this point the output is latched and the
DRAIN is no longer criticized. The latch is reset by any of the
signals that shut off the GATE (Over-Voltage, Under-Voltage;
Under-Voltage-Lock-Out; Over-Current Time-Out or
powering down). In this case the PWRGD/PWRGD output
will go inactive, indicating power is no longer good.
ISL6141 (L version; Figure 30): Under normal conditions
(DRAIN voltage - V_EE < V_PG, and ∆V_GATE - V_GATE < V_GH)
the Q2 DMOS will turn on, pulling PWRGD low, enabling the
module.
VDD
VIN+ VOUT+
∆ V_GATE
(SECTION OF) ISL6141
V_{GH -}
(L VERSION)
PWRGD
ON/OFF
GATE
+
V_PG
+
+
-
-
V_EE
LOGIC ^Q2
+
LATCH
+
ACTIVE LOW
CL
ENABLE
MODULE
V_{EE DRAIN}
VIN- ^VOUT-
FIGURE 30. ACTIVE LOW ENABLE MODULE
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