ISL6141 Datasheet, PDF (13/19 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6141, ISL6151
Inrush Current Control
The primary function of the ISL6141 hot plug controller is to
control the inrush current. When a board is plugged into a
live backplane, the input capacitors of the board’s power
supply circuit can produce large current transients as they
charge up. This can cause glitches on the system power
supply (which can affect other boards!), as well as possibly
cause some permanent damage to the power supply.
The key to allowing boards to be inserted into a live
backplane is to turn on the power to the board in a controlled
manner, usually by limiting the current allowed to flow
through a FET switch, until the input capacitors are fully
charged. At that point, the FET is fully on, for the smallest
voltage drop across it. Figure 25 below illustrates the typical
inrush current response resulting from a hot insertion for the
following conditions:
• V_EE = -48V, Rsense = 0.02Ω (2.5A current limit)
• C1 = 150nF, C2 = 3.3nF, R3 = 18kΩ
• I_Inrush = 50µA (100µF/3.3nF) = 1.5A
• C_L = 100uF, R_L = 150Ω (48V/150Ω = 320mA)
Electronic Circuit Breaker/Current Limit
The ISL6141/51 features programmable current limiting with a
fixed 600µs time-out period to protect against excessive
supply or fault currents. The IntelliTrip^TM electronic circuit
breaker is capable of detecting both hard faults, and less
severe Over-Current conditions.
The Over-Current trip point is determined by R1 (Eq. #3) also
referred to as Rsense. When the voltage across this resistor
exceeds 50mV, the current limit regulator will turn on, and the
GATE will be pulled lower (to ~4V) to regulate current through
the FET at 50mV/Rsense. If the fault persists and current
limiting exceeds the 600µs time-out period, the FET will be
turned off by discharging the GATE pin to V_EE. This will
enable the Over-Current latch and the PWRGD/PWRGD
output will transition to the inactive state to indicate power is
no longer good. To clear the latch and initiate a normal power-
up sequence, the user must either power down the system
(below the UVLO voltage), or toggle the UV pin below and
above its threshold (usually with an external transistor). Figure
26 below shows the Over-Current shut down and current
limiting response for a 10Ω short to ground on the output. With
FIGURE 25. INRUSH CURRENT LIMITING FOR A HOT
INSERTION
After the contact bounce subsides the UVLO and UV criteria
are quickly met and the GATE begins to ramp up. As the
GATE reaches approximately 4V with respect to the source,
the FET begins to turn on allowing current to charge the load
capacitor. As the drain to source voltage begins to drop, the
feedback network of C2 and R3 hold the GATE constant, in
this case limiting the current to approximately 1.3A. When
the DRAIN voltage completes its ramp down the load current
remains constant at 320mA as the GATE voltage increases
to its final value.
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FIGURE 26. CURRENT LIMITING AND TIMEOUT
a 10Ω short and a -48V supply, the initial fault current is
approximately 4.8A, producing a voltage drop across the
0.02Ω sense resistor of 95mV, roughly two times the Over-
Current threshold of 50mV. This enables the 600µs timer and
the GATE is quickly pulled low to limit the current to 2.5A
(50mV/Rsense). The fault condition persists for the duration of
the time-out period and the GATE is latched off in about
670µs. There is a short filter (3µs nominal) on the comparator,
so current transients shorter than this will be ignored. Longer
transients will initiate the GATE pull down, current limiting, and
the timer. If the fault current goes away before the time-out
period expires the device will exit the current limiting mode
and resume normal operation.