ISL78206 Datasheet, PDF (16/19 Pages) Intersil Corporation – 40V 2.5A Buck Controller with Integrated High-side 40V 2.5A Buck Controller with Integrated High-side

ISL78206
Power Stage Transfer Functions
Transfer function F₁(S) from control to output voltage is:
F₁S
=
v_{-ˆ-d-ˆ-o--}
=
1 + -----^S------
V_{i n} -_-S--------_2o2------+------_--------_o^--_S----_Q--^e-------^s_-p----^r--+-----₁-
(EQ. 12)
Where
_esr = -_R----_c-¹--_C-----_o- ,Q_p  R_o
C_-L---P-o-
,_o=
---------¹---------
L_PC_o
Transfer function F₂(S) from control to inductor current is given
by Equation 13:
F₂S = ^ˆ-Id-ˆ^o--
=
R^-----_o^----V-+---i-R^-n----_L^---_P^--
1 + --^S----
-_-S--------_2o2------+-----_{---------o}--_S----^_Q--------^z--_p------+-----₁-
(EQ. 13)
Where ^z ^{= -}_R^----_o^--1--_C^----_o^- .
Current loop gain T_i(S) is expressed as Equation 14:
T_iS = R_tF_mF₂SH_eS
(EQ. 14)
The voltage loop gain with open current loop is Equation 15:
T_vS = KF_mF₁SA_vS
(EQ. 15)
The Voltage loop gain with current loop closed is given by
Equation 16:
L_vS = -₁----^T_+----^v-_T--^--^S_i--_--_S-^----_
(EQ. 16)
If T_i(S)>>1, then Equation 16 can be simplified as Equation 17:
L_vS= ^R-----^o-----+_R----^R-_t----^L---^P-- ¹---₁--+---+--^{------------SSe}_----------^s------r _H-^A----^ve---^---^SS----^-_ , _p  -_R----_o--¹-_C-----_o-
_p
(EQ. 17)
Equation 17 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. While type III compensator is needed to
expand the bandwidth for current mode control in some cases.
R2
C1
R3
C3
V_COMP
V_O
V_REF
R1
R_BIAS
FIGURE 23. TYPE III COMPENSATOR
A compensator with 2 zeros and 1 pole is recommended for this
part as shown in Figure 23. Its transfer function is expressed as
Equation 18:
Where,
A_vS= ^v-ˆ---^c-_v-ˆ-^o--_O-^m-----^p- = _S-----_R----¹-₁---_C-----₁- ^---¹-----+------^-------_^-c-^S---₁--^z-------^{1-+--}---_--^_-----S1---_{c------p-+--}----^---------^{cS------z------2----}-
_cz1 = -_R----₂--¹-_C-----₁- , _cz2 = _---_R-----₁----+----¹-_R----₃----_--_C-----₃- _cp= -_R----₃--¹-_C-----₃-
Compensator design goal:
Loop bandwidth f_c:


14_--
t
o
1^--1--0^{--}
f_s
Gain margin: >10dB
(EQ. 18)
Phase margin: 45°
The compensator design procedure is as follows:
1. Position _CZ2 and _CP to derive R₃ and C₃.
Put the compensator zero _CZ2 at (1 to 3)/(R_oC_o)
_cz2 = -_R----_o--³-_C-----_o-
(EQ. 19)
Put the compensator pole _CP at ESR zero or 0.35 to 0.5 times
of switching frequency, whichever is lower. In all-ceramic-cap
design, the ESR zero is normally higher than half of the switching
frequency. R₃ and C₃ can be derived as following:
Case A: ESR zero -₂---_----_R--¹---_c---_C----_o-- less than (0.35 to 0.5) f_s
C₃ = ^R-----^o---^C-----^o--₃--–--_R---³-₁---^R----^c---^C-----^o-
R₃ = _R---³--_o--^R---–--^c--₃-^R---_R-¹---_c-
Case B: ESR zero -₂---_----_R--¹---_c---_C----_o-- larger than (0.35 to 0.5) f_s
C₃ = ⁰----^.--³---³----^R----^o--_f--^C_s---_R-^o----^f₁-^s-----–----⁰---^.--⁴---⁶--
R₃ = -₀---_.--₇---₃----_R----_o-^R---_C-¹---_o----_f-_s-----–----₁--
(EQ. 20)
(EQ. 21)
(EQ. 22)
(EQ. 23)
2. Derive R₂ and C₁.
The loop gain L_v(S) at cross over frequency of f_c has unity gain.
Therefore, C₁ is determined by Equation 24.
C₁ = ₂-^--^R-_----¹_f--_c--+-_R----^R-_t--_R--³--₁-^--^C-_C----^3o-
(EQ. 24)
The compensator zero _CZ1 can boost the phase margin and
bandwidth. To put _CZ1 at 2 times of cross cover frequency f_c is a
good start point. It can be adjusted according to specific design.
R₁ can be derived from Equation 25.
R₂ = ₄----_----_f-¹-_c---_C-----₁-
(EQ. 25)
Example: V_IN = 12V, V_O = 5V, I_O = 2A, f_s = 500kHz,
C_o = 60µF/3mΩ, L = 10µH, R_t = 0.20V/A, f_c = 50kHz,
R₁ = 105k, R_BIAS = 20kΩ.
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FN8618.2
March 25, 2015