ISL78206 Datasheet, PDF (14/19 Pages) Intersil Corporation – 40V 2.5A Buck Controller with Integrated High-side 40V 2.5A Buck Controller with Integrated High-side

ISL78206
Fault Protection
Overcurrent Protection
The overcurrent function protects against any overload conditions
and output shorts at worst case, by monitoring the current
flowing through the upper MOSFET.
There are 2 current limiting thresholds. The first one, I_OC1, is to
limit the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set to a default of 3.6A with the ILIMIT
pin connected to GND or VCC, or left open. The current limit
threshold can also be programmed by a resistor R_LIM at ILIMIT
pin to ground. Use Equation 3 to calculate the resistor.
R_LIM = _I--_O-----_C----³_---_A0----⁰_---⁰-+--⁰--₀--⁰--_.-₀----₁---₈--
(EQ. 3)
Note that with the lower R_LIM, IOC1 is higher. The usable resistor
value range to program OC1 peak current threshold is 40kΩ
to 330kΩ. R_LIM value out of this range is not recommended.
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40 ₀
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
I_OC1 (A)
FIGURE 21. R_LIM vs I_OC1
The second current protection threshold, I_OC2, is 15% higher
than I_OC1 mentioned above. Upon the instant that the high-side
MOSFET current reaches I_OC2, the PWM shuts off after 2 cycle
delay and the IC enters hiccup mode. In hiccup mode, the PWM
is disabled for dummy soft-start duration equaling 5 regular
soft-start periods. After this dummy soft-start cycle, the true
soft-start cycle is attempted again. The I_OC2 offers a robust and
reliable protection against worst case conditions.
The frequency foldback is implemented for the ISL78206. When
overcurrent limiting, the switching frequency is reduced to be
proportional to the output voltage in order to keep the inductor
current under limit threshold during overload conditions. The low
limit of frequency under frequency foldback is 40kHz.
Overvoltage Protection
If the voltage detected on the FB pin is over 110% or 120% of
reference, the high-side and low-side driver shuts down
immediately and keep off until FB voltage drops to 0.8V. When
the FB voltage drops to 0.8V, the drivers are released ON. 110%
OVP is off at soft-start and becomes active after soft-start is
done. 120% OVP is active before and after soft-start.
Thermal Protection
The ISL78206 PWM will be disabled if the junction temperature
reaches +160°C. There is +20°C hysteresis for OTP. The part will
restart after the junction temperature drops below +140°C.
Component Selection
The ISL78200 iSim model (buck mode), available on the internet
(ISL78200 iSim), and can be used to simulate the ISL78206
behaviors to assist in design.
Output Capacitors
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
Additional consideration applies to ceramic capacitors. While they
offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors are
rated using large peak-to-peak voltage swings and with no DC bias.
In the DC/DC converter application, these conditions do not reflect
reality. As a result, the actual capacitance may be considerably
lower than the advertised value. Consult the manufacturers data
sheet to determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, but an assumption of ~20% further
reduction will generally suffice. The result of these considerations
can easily result in an effective capacitance 50% lower than the
rated value. Nonetheless, they are a very good choice in many
applications due to their reliability and extremely low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR):
V_OUTripple=
----------------^----^I----------------
8^ f_{S W}^ C_{O U T}
(EQ. 4)
Where I is the inductor’s peak-to-peak ripple current, f_SW is the
switching frequency and C_OUT is the output capacitor.
If using electrolytic capacitors then:
V_OUTripple= I*ESR
(EQ. 5)
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FN8618.2
March 25, 2015