ISL6296_07 Datasheet, PDF (16/19 Pages) Intersil Corporation – FlexiHash™ For Battery Authentication

ISL6296
ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET
SET #2 (SE2A/B/C/D)
These address locations store the second set of secrets to
be used for hash calculation. Reading and writing to this
register can be disabled by setting the SLO[1] bit at OTP
ROM location 0-00[1].
ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET
SET #3 (SE3A/B/C/D)
These address locations store the optional third set of
secrets to be used for hash calculation. Reading and writing
to this register can be disabled by setting the SLO[0] bit at
OTP ROM location 0-00[0].
Alternately, this memory space can be used to store
additional cell information which can be accessed by the
host. In this case, the SLO[0] bit should not be set.
BIT NAME
7
eEEW
6
eINT
5:2
--
1
ASLP
0
SRST
TYPE
R
RW
R
RW
WC
TABLE 14. MASTER CONTROL REGISTER (MSCR)
DEFAULT
DESCRIPTION
0
<1/0>
OTP ROM Write-in-Progress Interrupt Enable: When enabled, it allows the sEEW bit to flag an
interrupt whenever the sEEW bit is set by its interrupt event. The eEEW bit is fixed at ‘1’ when none
of the OTP ROM lock-out bits is set. When any or both of the lock-out bits are set, the eEEW bit will
become permanently ‘0’ after a reset.
0
Global Interrupt Enable: When enabled, it allows the sBER or sACC bit to flag an interrupt to the
<1> host whenever any of the respective interrupt event occurred.
(Default setting loaded from OTP ROM location 0-00[3])
0
Unused.
0
Auto Sleep Mode enable: When set, the ISL6296 will automatically enter Sleep mode after about
<1> 1s of XSD bus inactivity. When cleared, the device can only enter Sleep mode on Opcode
command.
(Default setting loaded from OTP ROM location 0-00[2])
0
Soft Reset: When a ‘1’ is written, and all registers are reset to their default states, all bus counters
and timers are reset to their start-up conditions, and device configuration information is reloaded
from OTP ROM. After the reset sequence is completed, a ‘break’ pulse is sent to the host.
BIT
NAME
7
sEEW
6
sBER
5
sACC
4
--
3:2 DAB[1:0]
1:0 SLO[1:0]
TYPE
RC
RC
RC
R
R
R
TABLE 15. DEVICE STATUS REGISTER (STAT)
DEFAULT
DESCRIPTION
0
OTP ROM Write-in-Progress Flag: This bit is set when attempt is made by the host to read from or
write to the ISL6296 while the ROM is still processing the previous write instruction.
0
XSD Bus Error Flag: This bit is set when one or more of the following occurred at the bus interface:
a) An invalid pulse width is received
b) Bus activity is detected before the device completes its power-up sequence
c) An invalid BYTES field in the instruction frame
d) Improper authentication sequence is detected
e) Reading secret information after the corresponding lock-out bits are set
0
Register Access Error Flag: This bit is set whenever an instruction frame attempts to access a
protected register as follows:
a) Writing to OTP ROM after the ISL6296 has been locked out (any or both of the lock-out bits set)
b) Accessing the ISL6296ís Test and Trim Registers when the device is not in test mode
0
Unused
00
<00>
Device Address Bit Setting:
Loaded from OTP ROM location 0-00[7:6] during power-up.
00
<00>
Secrets Lock-out Bits Setting:
Loaded from OTP ROM location 0-00[1:0] during power-up.
16
FN9201.1
January 17, 2007