ISL6296_07 Datasheet, PDF (12/19 Pages) Intersil Corporation – FlexiHash™ For Battery Authentication

ISL6296
15
0
BYTES
ADDRESS
BANK OPCODE CS
FIGURE 10. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION
TABLE 4. DEFINITION OF THE OPCODE FIELD
OPCODE
DESCRIPTION
ACTION
00
Write Operation
Write to device register
01
Read Operation (normal) Read from device register
10
Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the last read frame.
11
Sleep Mode Activation
Immediately sets the device in Sleep mode.
Note: After detecting the ‘11’ Opcode, the device immediately enters sleep mode. If more than 3
bits sent, subsequent pulses may wake the device up again.
Access Instruction Frame
The XSD access instruction frame is shown in Figure 10.
The instruction frame consists of 16 bits of digital signal with
the contents described as following.
CS FIELD
The CS field is a 1-Bit Chip Address Selection. An initial
1-Bit Chip Address code of ‘0’ is pre-programmed into the
device’s OTP ROM address location 0-00[7:6] at the time of
chip manufacture, and may be re-programmed by the pack
manufacturer if needed. If the CS code in the instruction
does not match the device’s Chip Address code, the
instruction, and any subsequent frames that follow, will be
ignored until a break command is received.
OPCODE FIELD
The OPCODE is a 2-Bit field defines the operation of the
transaction following the instruction frame. The operations
are described in Table 4.
BANK FIELD
The memories in the ISL6296 are divided into four banks.
The BANK field is defined in Table 5.
TABLE 5. BANK FIELD DEFINITION.
BANK
MEMORY/REGISTER BANK SELECTION
00 OTP ROM
01 Control and Status Registers
10 Device Authentication Registers
11 Test Registers (Reserved)
ADDRESS FIELD
The address field indicates the starting address of a memory
or register read or write sequence. Keep in mind that only odd
starting addresses are allowed for the OTP ROM access.
BYTES FIELD
The bytes field indicates the number of data bytes to read or
write, not including the CRC byte. Not all BYTES Field
settings are supported. Only settings marked with an ‘X’ is
valid for a particular bus instruction, as indicated in Table 6.
Attempt to read or write with an invalid BYTES setting may
yield unpredictable results.
Writing to OTP ROM can occur at only two bytes at a time,
but reading from OTP ROM can happen at 2, 4 or 16 bytes
at a time. Writing to and reading from OTP ROM in any other
byte denomination will yield unpredictable result, and should
therefore be strictly prohibited.
BYTES
FIELD
0
1
2
3
4
5-6
7
TABLE 6. DEFINITION OF THE BYTES FIELD
DATA BYTES OTP ROM OTP ROM REG READ CHLG CODE
TO FOLLOW WRITE
READ OR WRITE
WRITE
COMMENTS
0
Invalid selection. Causes a bus error.
1
X
Must use 1-Byte read for clearing of the STAT register.
2
X
X
X
N/A
Invalid selection. Causes a bus error.
4
X
X
N/A
Invalid selection. Causes a bus error.
16
X
For reading from OTP ROM only (prior to lock-out).
12
FN9201.1
January 17, 2007