ISL26132 Datasheet, PDF (16/23 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

PARAMETER
t₂
t₃
t₄
t₅
t₆
t₇
ISL26132, ISL26134
TABLE 10. INTERFACE TIMING CHARACTERISTICS
DESCRIPTION
MIN
TYP
SDO/RDY Low to first SLK
0
SCLK pulsewidth, Low or High
100
SCLK High to Data Valid
Data Hold after SCLK High
0
Register Update Time
39
Conversion Period
SPEED = 1
12.5
SPEED = 0
100
DATA READY
DATA
MAX
UNITS
ns
ns
50
ns
ns
µs
ms
ms
NEW DATA READY
SDO/RDY
SCLK
23
22
21
1
0
24
25
25TH SCLK FORCES
SDO/RDY HIGH
FIGURE 31. OUTPUT DATA WAVEFORMS FOR SDO/RDY POLLING
DATA READY AFTER CALIBRATION
SDO/RDY
23 22 21
0
23
CALIBRATION BEGINS
SCLK
1
24 25 26
t₈
FIGURE 32. OFFSET CALIBRATION WAVEFORMS
STANDBY MODE
DATA READY
SDO/RDY
SCLK
23 22 21
0
1
24
t₉
t₁₀
23
START
CONVERSION
t₁₁
FIGURE 33. STANDBY MODE WAVEFORMS
Offset Calibration Control
The offset internal to the ADC can be removed by performing an
offset calibration operation. Offset calibration can be initiated
immediately after reading a conversion word with 24 SCLKs by
issuing two additional SCLKs. The offset calibration operation will
begin immediately after the 26th SCLK occurs. Figure 32
illustrates the timing details for the offset calibration operation.
During offset calibration, the analog inputs are shorted internally
and a regular conversion is performed. This conversion generates
a conversion word that represents the offset error. This value is
stored and used to digitally remove the offset error from future
conversion words. The SDO/RDY output will fall to indicate the
completion of the offset calibration operation.
TABLE 11. SDO/RDY DELAY AFTER CALIBRATION
PARAMETER
MIN
MAX
t₈
SPEED = 1
108
109
SPEED = 0
808
809
UNITS
ms
ms
16
FN6954.1
September 9, 2011