ISL26132 Datasheet, PDF (13/23 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26132, ISL26134
AINx+
+
A1
-
R_F1
R₁
R_F2
CAP
R_INT
ADC
AINx-
-
A2
+
R_INT
CAP
FIGURE 24. SIMPLIFIED PROGRAMMABLE GAIN AMPLIFIER BLOCK DIAGRAM
Filtering PGA Output Noise
The programmable gain amplifier, as shown in Figure 24,
includes a passive RC filter on its output. The resistors are
located inside the chip on the outputs of the differential amplifier
stages. The capacitor (nominally a 100nF C0G ceramic or a PPS
film (Polyphenylene sulfide)) for the filter is connected to the two
CAP pins of the chip. The outputs of the differential amplifier
stages of the PGA are filtered before their signals are presented
to the delta-sigma modulator. This filter reduces the amount of
noise by limiting the signal bandwidth and filters the chopping
artifacts of the chopped PGA stage.
Voltage Reference Inputs (VREF+, VREF-)
The voltage reference for the ADC is derived from the difference
in the voltages presented to the VREF+ and VREF- pins;
VREF = (VREF+ - VREF-). The ADCs are specified with a voltage
reference value of 5V, but a voltage reference as low as 1.5V can
be used. For proper operation, the voltage on the VREF+ pin
should not be greater than AVDD + 0.1V and the voltage on the
VREF- pin should not be more negative than AGND - 0.1V.
Clock Sources
The ISL26132, ISL26134 can operate from an internal oscillator,
an external clock source, or from a crystal connected between
the XTALIN/CLOCK and XTALOUT pins. See the block diagram of
the clock system in Figure 25. When the ADC is powered up, the
CLOCK DETECT block determines if an external clock source is
present. If a clock greater than 300kHz is present on the
XTALIN/CLOCK pin, the circuitry will disable the internal oscillator
on the chip and use the external clock as the clock to drive the
chip circuitry. If the ADC is to be operated from the internal
oscillator, the XTALIN/CLOCK pin should be grounded.
If the ADC is to be operated from a crystal, it should be located
close to the package pins of the ADC. Note that external loading
capacitors for the crystal are not required as there are loading
capacitors built into the silicon, although the capacitor values are
optimized for operation with a 4.9152MHz crystal.
The XTALOUT pin is not intended to drive external circuits.
XTALIN/
CLOCK
CRYSTAL
OSCILLATOR
CLOCK DETECT
XTALOUT
INTERNAL
EN
OSCILLATOR
MUX
TO ADC
FIGURE 25. CLOCK BLOCK DIAGRAM
Digital Filter Characteristics
The digital filter inside the ADC is a fourth-order Siinc filter.
Figures 26 and 27 illustrate the filter response for the ADC when
it is operated from a 4.9152MHz crystal. The internal oscillator is
factory trimmed so the frequency response for the filter will be
much the same when using the internal oscillator. The figures
illustrate that when the converter is operated at 10Sps the digital
filter provides excellent rejection of 50Hz and 60Hz line
interference.
13
FN6954.1
September 9, 2011