ISL26132 Datasheet, PDF (14/23 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26132, ISL26134
0
DATA RATE = 10 SSpPsS
-50
-100
-150
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz
-50
-60
DATA RATE = 10Sps
-70
-80
-90
-100
-110
-120
-130
-140
-150
45
50
55
60
65
FREQUENCY (Hz)
FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz
Serial Clock Input (SCLK)
The serial clock input is provided with hysteresis to minimize
false triggering. Nevertheless, care should be taken to ensure
reliable clocking.
Filter Settling Time and ADC Latency
Whenever the analog signal into the ISL26132, ISL26134
converters is changed, the effects of the digital filter must be
taken into account. The filter takes four data ready periods for
the output code to fully reflect a new value at the analog input. If
the multiplexer control input is changed, the modulator and the
digital filter are reset, and the device uses four data ready
periods to fully settle to yield a digital code that accurately
represents the analog input. Therefore, from the time the control
inputs for the multiplexer are changed until the SDO/RDY goes
low, four data ready periods will elapse. The settling time delay
after a multiplexer channel change is listed in Table 8 for the
converter operating in continuous conversion mode.
PARAMETER
t_S
t1
TABLE 8. SETTLING TIME
DESCRIPTION
(f_CLK = 4.9152MHz)
MIN
A0, A1, SPEED, Gain1, Gain0 change
40
set-up time
Settling time
SPEED = 1
54
SPEED = 0
404
A0, A1, SPEED, Gain1, Gain0
SDO/RDY
t₁
t_S
FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
MAX
50
55
405
UNITS
µs
ms
ms
14
FN6954.1
September 9, 2011