ISL12082 Datasheet, PDF (16/26 Pages) Intersil Corporation – I2C-Bus™ Real Time Clock with Two Interrupts, Alarm, and Timer

ISL12082
Sub-Timer Initial Register (TSDAT, address 14h) is set to “0”,
the number of counts changes to the default value. The
maximum register value for the TSDAT register is 127 which
means the maximum limit for the internal Sub-Timer Counter
Register is also 127. See Table 10 for Timer/Watchdog clock
frequency selection and the default counts for the Sub-Timer
Counter Register.
TABLE 10. TIMER CLOCK FREQUENCY SELECTION AND
DEFAULT VALUE FOR TSDAT REGISTER
TCLK1 TCLK0 FUNCTION
COMMENT
0
0 100Hz/4kHz 100Hz for TCNT, 4kHz for TSCNT
Default Value for TSDAT = 41
(41 TSCNT counts = 1ms)
(Not available for Watchdog Timer)
0
1 1sec/100Hz 1sec for TCNT, 100Hz for TSCNT
Default Value for TSDAT = 100
(100 TSCNT counts = 1s)
1
0 1min/1sec 1min for TCNT, 1sec for TSCNT
Default Value for TSDAT = 60
(60 TSCNT counts = 1min)
(RTC must be enabled)
1
1 1hr/1min 1hour for TCNT, 1min for TSCNT
Default Value for TSDAT = 60
(60 TSCNT counts = 1hr)
(RTC must be enabled)
The Timer Counter and Sub-Timer Counter Registers
advance the counter value based on the frequency or time
setting by the TCLK<1:0> bits.
The following are examples of Timer clock frequency
selection bits on Timer Counter and Sub-Timer Counter
Registers.
Example 1 - TCLK1 is set to “1”, TCLK0 is set to “0”, and
Sub-Timer Initial Register is set to “0”. The internal
Sub-Timer Counter will increment every 1s. When the
internal Sub-Timer Counter reaches to 60, the default value,
the Timer Counter will increment by one which means the
Timer Counter will increment every one minute.
Example 2- TCLK1 is set to “1”, TCLK0 is set to “0”, and
Sub-Timer Initial Register is set to “10d”. The internal
Sub-Timer Counter will increment every 1s. When the
internal Sub-Timer Counter reaches to 10, the Timer
Counter will increment by one which means the Timer
Counter will increment every ten seconds.
Example 3- TCLK1 is set to “0”, TCLK0 is set to “1”, and
Sub-Timer Initial Register is set to “0”. The internal
Sub-Timer Counter will increment every 1ms (100Hz). When
the internal Sub-Timer Counter reaches to 100, the default
value2, the Timer Counter will increment by one which
means the Timer Counter will increment every one second.
TIMER FUNCTION SELECTION BITS (TMOD <1:0>)
The Timer interrupt has four different functions:
1. Count Down Timer
2. Secondary Alarm Timer
3. Watchdog Timer
4. Power Fail Count-up Timer
Please see Table 11 for Timer counting functions selection.
TABLE 11. TIMER COUNTING FUNCTION SELECTION
TMOD1 TMOD0 FUNCTION
COMMENT
0
0 Count Down Basic count down timer
Timer
(TCNT register decrement)
0
1 Secondary Basic count down timer activated by
Alarm Timer ALARM IRQ (ALM bit)
(TCNT register decrement)
1
0 Watchdog Count up timer with periodic
Timer
interrupt
(TCNT register increment)
1
1 Power Fail Count up after device entered into
Count-up
battery mode
Timer
(TCNT register increment)
TIMER ENABLE BIT (TMRE)
This bit enables/disables the timer function. When the TMRE
bit is set to “1”, the timer is enabled. To display timer interrupt
on the IRQ2 pin, the IRQ2E has to be set to “1”. When the
TMRE bit is cleared to “0”, the timer function is disabled. The
TMRE bit is set to “0” on power-up.
TIMER PULSE/EVENT INTERRUPT BIT (TIM)
This bit enables/disables the interrupt mode of the timer
function. When the TIM bit is set to “1”, the timer will operate
in the interrupt mode. An active low pulse width of 210ms will
appear at the IRQ2 pin when the RTC is triggered by the
timer as defined by the timer registers (12h to 15h). When
the TIM bit is cleared to “0”, the timer will operate in standard
mode, where the IRQ2 pin will be held low until TMR status
bit is cleared to “0”. The TIM bit is set to “0” on power-up.
TIM BIT TIMER PULSE/EVENT INTERRUPT FUNCTION
0
Single Time Event Set By Timer
1
Repetitive/Recurring Time Event Set By Timer
Timer Registers
Addresses [12h to 15h]
Timer Initial Register (TDAT) [Address 12h]
The Timer Initial Register is located in the memory map at
address 12h. This is a volatile register that stores the timer
limit for the timer counter register.
TABLE 12. TIMER INITIAL REGISTER (TDAT)
ADDR 7
6
5
4
3
2
1
0
12h TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0
Default 0
0
0
0
0
0
0
0
16
FN6731.3
November 24, 2008