ISL12082 Datasheet, PDF (14/26 Pages) Intersil Corporation – I2C-Bus™ Real Time Clock with Two Interrupts, Alarm, and Timer

ISL12082
IM BIT ALARM PULSE/EVENT INTERRUPT FUNCTION
1
Repetitive/Recurring Time Event Set By Alarm
Analog Trimming Register (ATR) [Address 0Ah]
TABLE 7. ANALOG TRIMMING REGISTER (ATR)
ADDR 7
6
543210
0Ah BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
Default 0
0
000000
ANALOG TRIMMING REGISTER (ATR<5:0>)
X1
C_X1
X2
C_X2
CRYSTAL
OSCILLATOR
FIGURE 11. DIAGRAM OF ATR
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to
-97ppm to +206ppm of total adjustment.
The effective on-chip series load capacitance, C_LOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C_LOAD is changed via two digitally
controlled capacitors, C_X1 and C_X2, connected from the X1
and X2 pins to ground (see Figure 11). The value of C_X1 and
C_X2 are given in Equation 1:
CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF ^{(EQ. 1)}
The effective series load capacitance is the combination of
C_X1 and C_X2 in Equation 2:
CLOAD
=
----------------¹------------------
⎛
⎝
-----¹-----
C_X1
+
C^-----1_X^----₂^{-⎠⎞}
(EQ. 2)
CLOAD
=
⎛
⎝
1_---6_-----⋅_---b_---5_----+_-----8_----⋅_---b_---4_-----+_----4_----⋅_---b_----3_----+_----2_-2----⋅_---b_---2_----+_----1_-----⋅_---b_---1_----+_-----0_---._-5_----⋅_----b_---0_----+_----9_{--⎠⎞}
p
F
For example, C_LOAD(ATR = 00000) = 12.5pF, C_LOAD
(ATR = 100000) = 4.5pF and C_LOAD (ATR = 011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the V_DD/V_BAT operation, the ISL12082 provides the
capability to adjust the capacitance between V_DD and V_BAT
when the device switches between power sources.
BMATR1
0
0
1
1
BMATR0
0
1
0
1
DELTA
CAPACITANCE
(C_BAT TO C_VDD)
0pF
-0.5pF (≈ +2ppm)
+0.5pF (≈ -2ppm)
+1pF (≈ -4ppm)
Digital Trimming Register (DTR) [Address 07h]
TABLE 8. DIGITAL TRIMMING REGISTER (DTR)
ADDR 7
6
543210
07h
0
0 DTR5 DTR4 DTR3 DTR2 DTR1 DTR0
Default 0
0
000000
DIGITAL TRIMMING REGISTER (DTR<5:0>)
Six digital trimming bits, DTR0 to DTR5, are provided to
adjust the average number of counts per second and
average the ppm error to achieve better accuracy.
• DTR5 is a sign bit. DTR5 = “0” means frequency
compensation is < 0. DTR5 = “1” means frequency
compensation is > 0.
• DTR<4:0> are scale bits. With DTR5 = “0”, DTR<4:0>
gives 2.0345ppm adjustment per step. With DTR5 = “1”,
DTR<4:0> gives 4.0690ppm adjustment per step.
A range from -63.0696ppm to +126.139ppm can be
represented by using these 6 bits.
For example, with DTR = 11111, the digital adjustment is
(1111b[15d]*4.0690) = +126.139ppm. With DTR = 01111, the
digital adjustment is (-(1111b[15d]*2.0345)) = -63.0696ppm.
Alarm Registers
Addresses [Address 0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc) are used to make the
comparison. Note that there is no alarm byte for year and
sub-second, and the register order for alarm register is not a
100% matching to the RTC register so please take caution
on programming the alarm function.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
14
FN6731.3
November 24, 2008