ISL12082 Datasheet, PDF (12/26 Pages) Intersil Corporation – I2C-Bus™ Real Time Clock with Two Interrupts, Alarm, and Timer

ISL12082
Real Time Clock Registers
Addresses [00h to 06h, and 1Fh]
RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR, SS)
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes,
address 01h) range from 0 to 59, HR (Hour, address 02h)
can either be a 12-hour or 24-hour mode, DT (Date, address
03h) is 1 to 31, MO (Month, address 04h) is 1 to 12, YR
(Year, address 05h) is 0 to 99, DW (Day of the Week,
address 03h) is 0 to 6, and SS (Sub-Seconds/Hundredths of
a Second, address 1Fh) is 0 to 99. The SS register is read
only. A Page read operation to read all the RTC regsiters is
possible by setting up the address to 1Fh then do a page
read of 8 bytes. The first data read will be SS, then follows
by SC, MN, HR, DT, MO, YR, and DW at the end. This is
done by using address wrap around feature of the ISL12082.
The address wraps around from 1Fh to 00h in page read
instruction.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
Bit D7 of MN register contains the Oscillator Fail Indicator bit
(OF). This bit is set to a “1” when there is no oscillation on X1
pin. The OF bit can only be reset by having an oscillation on
X1 and a write operation to reset it.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a 24-
hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour
formattime with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
ISL12082 does not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt and alarm register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR) [Address 07h]
The Status Register is located in the memory map at
address 0Bh. This is a volatile register that provides either
control or status of RTC failure, battery mode, alarm trigger,
write protection of clock counter, crystal oscillator enable and
auto reset of status bits.
TABLE 2. STATUS REGISTER (SR)
ADDR 7
6
5
4
3 21 0
07h ARST XSTOP RESEAL WRTC TMR ALM BAT RTCF
Default 0
0
1
0
0 01 1
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12082 internally) when
the device powers up after having lost all power (both V_DD
and V_BAT go to 0V). The bit is set regardless of whether V_DD
or V_BAT is applied first. The loss of only one of the supplies
does not set the RTCF bit to “1”. On power-up after a total
power failure, all registers are set to their default states and
the clock will not increment until at least one byte is written to
the clock register. The first valid write to the RTC section
after a complete power failure resets the RTCF bit to “0”
(writing one byte is sufficient).
BATTERY BIT (BAT)
This bit is set to a “1” when the device enters battery backup
mode. This bit can be reset either manually by the user or
automatically reset by enabling the auto-reset bit (see ARST
bit). A write to this bit in the SR can only set it to “0”, not “1”.
ALARM BIT (ALM)
This bit announces that the alarm matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit can be manually reset to “0” by the user or automatically
reset by enabling the auto-reset bit (see ARST bit). A write to
this bit in the SR can only set it to “0”, not “1”.
Note: An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read operation is
complete.
TIMER BIT (TMR)
This bit announces that the timer has expired. If the timer
has expired, the respective bit is set to “1”. This bit can be
manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit
in the SR can only set it to “0”, not “1”.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
ReSeal™ (RESEAL)
The ReSeal™ enables the device enter into the InterSeal™
Battery Saver mode after board functional testing. The factory
12
FN6731.3
November 24, 2008