ISL12082 Datasheet, PDF(13/26 Page) Intersil Corporation – I2C-Bus™ Real Time Clock with Two Interrupts, Alarm, and Timer

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ISL12082 Datasheet, PDF (13/26 Pages) Intersil Corporation – I2C-Bus™ Real Time Clock with Two Interrupts, Alarm, and Timer

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ISL12082

default setting of this bit is â0â to enable the backup battery

operation. To use the ReSealâ¢ function, simply set RESEAL

bit to â1â after the testing is completed. It will enable the

InterSealâ¢ Battery Saver mode and prevents battery current

drain before it is first used. Upon the next VDD powerup, the

bit will reset to â0â and the backup battery will be utilized.

CRYSTAL OSCILLATOR ENABLE BIT (XSTOP)

This bit enables/disables the crystal oscillator. When the

XSTOP is set to â1â, the oscillator is disabled. The XSTOP

bit is set to â0â on power-up for normal operation.

AUTO RESET ENABLE BIT (ARST)

This bit enables/disables the automatic reset of the BAT,

ALM and TMR status bits only. When ARST bit is set to â1â,

these status bits are reset to â0â after a valid read of the

respective status register (with a valid STOP condition).

When the ARST is cleared to â0â, the user must manually

reset the BAT, ALM and TMR bits.

Interrupt Control Register (INT) [Address 08h]

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

ADDR 7 6

2 10

08h IM ALME LPMODE FOBATB IRQ2E IRQ1E FO1 FO0

Default 0 0

0 00

FREQUENCY OUT CONTROL BITS (FO <1:0>)

These bits select the output frequency at the IRQ/fOUT pin.

IRQ1E must be set to â0â for frequency output at the

IRQ/fOUT pin. See Table 4 for frequency selection.

TABLE 4. FREQUENCY SELECTION OF fOUT PIN

FREQUENCY,

fOUT

UNITS FO1

32768

FO0

COMMENT

0 Free running

crystal clock

4096

1 Free running

crystal clock

512

0 Free running

crystal clock

1 Sync. with

second, 30Âµs jitter

Note: The falling edge of 1Hz frequency output is

synchronized with the seconds.

IRQ FUNCTION SELECTION BITS (IRQ1E, IRQ2E)

These bits select the function of IRQ1/fOUT and IRQ2 pin.

See Table 5 for function selection of IRQ1/fOUT pin and

Table 6 for function selection of IRQ2 pin.

TABLE 5. FUNCTION SELECTION OF IRQ1/fOUT

IRQ1/fOUT FUNCTION

fOUT

IRQ2E

IRQ1E

TABLE 5. FUNCTION SELECTION OF IRQ1/fOUT

PIN (Continued)

IRQ1/fOUT FUNCTION

ALARM IRQ

IRQ2E

IRQ1E

TABLE 6. FUNCTION SELECTION OF IRQ2 PIN

IRQ2 FUNCTION

IRQ2E

IRQ1E

ALARM IRQ

TIMER IRQ

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables the IRQ1/fOUT pin during battery

backup mode (i.e. VBAT power source active). When the

FOBATB is set to â1â, the IRQ1/fOUT pin is disabled during

battery backup mode. This means that both the frequency

output and alarm output functions are disabled. When the

FOBATB is cleared to â0â, the IRQ1/fOUT pin is enabled

during battery backup mode.

LOW POWER MODE BIT (LPMODE)

This bit enables/disables low power mode. With

LPMODE = â0â, the device will be in normal mode and the

VBAT supply will be used when VDD < VBAT - VBATHYS and

VDD < VTRIP. With LPMODE = â1â, the device will be in low

power mode and the VBAT supply will be used when

VDD < VBAT - VBATHYS. There is a supply current saving of

about 600nA when using LPMODE = â1â with VDD = 5V (See

âTypical Performance Curvesâ on page 7: IDD vs VCC with

LPMODE ON and OFF). see also âPower Control Operationâ

under âFunctional Descriptionâ on page 9.

ALARM ENABLE BIT (ALME)

This bit enables/disables the alarm function. When the ALME

bit is set to â1â, the alarm function is enabled. When the ALME

is cleared to â0â, the alarm function is disabled. The alarm

function can operate in either a single event alarm or a periodic

interrupt alarm (see IM bit).

Note: When the frequency output mode is enabled, the alarm

function is disabled.

ALARM PULSE/EVENT INTERRUPT BIT (IM)

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to â1â, the alarm will operate

in the interrupt mode, where an active low pulse width of

210ms will appear at the IRQ1/fOUT and/or IRQ2 pin when

the RTC is triggered by the alarm as defined by the alarm

registers (0Ch to 11h). When the IM bit is cleared to â0â, the

alarm will operate in standard mode, where the IRQ1/FOUT

and/or IRQ2 pin will be tied low until the ALM status bit is

cleared to â0â. The IM bit is set to â0â on power-up.

IM BIT

ALARM PULSE/EVENT INTERRUPT FUNCTION

Single Time Event Set By Alarm

FN6731.3

November 24, 2008

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