ISL6442 Datasheet, PDF (15/16 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6442
LCDR
LCFB
R307
Q300
VIN3
C_IN3
R300
C300
R301
V_OUT3
R302
C_OUT3
FIGURE 16. LINEAR COMPENSATION COMPONENTS
Strategy
1. The output capacitor of the linear regulator circuit must be
chosen such that the ESR Zero is less than 200kHz:
F_Z1 < 200kHz
(EQ. 30)
2. The voltage divider can be chosen to sink 250µA to
1.5mA of sense current, but this is simply a guideline, not
a rule. The values should be chosen such that
R 301
=
V_{-----O----U----T----3----–-----}0_---._--6_----V_--
I_sen
(EQ. 31)
R 302
=
0_----._--6_---V_---
I_sen
(EQ. 32)
where I_sen = is the current through the resistor divider,
and 0.6V is the internal voltage reference that LCFB will
equal.
3. Compute the pole and zero for the linear regulator circuit
from Equations 31 and 32.
4. Make:
F_P2
=
-^F---^Z----¹-
10
(EQ. 33)
5. Fix R300 at 100Ω. Solve for C300. Use an MLCC, COG
or NPO type capacitor for this value.
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 17 shows the critical power components of the
converter. To minimize the voltage overshoot, the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 17 should be located as close
together as possible. Please note that the capacitors C_IN
and C_OUT each represent numerous physical capacitors.
Locate the ISL6442 within 1 inch of the MOSFETs, Q1 and
Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6442 must be sized to handle up to
2A peak current.
15
V_IN
ISL6442
UGATE
PHASE
LGATE
PGND
Q1
L_OUT
V_OUT
C_IN
Q2
C_OUT
RETURN
FIGURE 17. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
C_VCC
R_RT C_SS
VCC
BOOT
C_{BOOT CIN}
ISL6442
SS ^PHASE
RT
VIN
+V_IN
SGND PGND
C_VIN
SGND
+V_IN
Q1 _LOUT
V_OUT
Q2 ^COUT
PGND
FIGURE 18. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 18 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Locate the RT resistor as
close as possible to the RT pin and the SGND pin. Provide
local decoupling between VCC and GND pins.
For each switcher, minimize any leakage current paths on
the SS/EN pin and locate the capacitor, C_SS close to the
SS/EN pin because the internal current source is only 30µA.
All of the compensation network components for each
switcher should be located near the associated COMP and
FB pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins (but keep the noisy PHASE
plane away from the IC (except for the PHASE pin
connection).
The OCSET circuits (see Figure 2) should have a separate
trace from the upper FET to the OCSET R and C; that will
more accurately sense the VIN at the FET than just tying
them to the VIN plane. The OCSET R and C should be
placed near the IC pins.
FN9204.2
October 31, 2008