ISL6442 Datasheet, PDF (14/16 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6442
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
---------------¹----------------
2π ⋅ R2 ⋅ C1
(EQ. 19)
F_Z2 = ₂----_π-----_â‹---₍---_R----₁-----+-¹----_R-----₃----₎---_â‹---_C-----₃--
(EQ. 20)
F_P1 = ₂----_π-----_â‹---_R-----₂-----_⋹-----_{C----------1---------â‹}------_C----------₂------
C1 + C2
(EQ. 21)
F_P2 = ₂----_π-----_â‹---_R---¹--₃-----_â‹---_C-----₃-
(EQ. 22)
Figure 15 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previously mentioned guidelines
should yield a compensation gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 against the
capabilities of the error amplifier. The closed loop gain, G_CL, is
constructed on the log-log graph of Figure 15 by adding the
modulator gain, G_MOD (in dB), to the feedback compensation
gain, G_FB (in dB). This is equivalent to multiplying the
modulator transfer function and the compensation transfer
function and then plotting the resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log
⎛
⎝
RR-----21--_⎠⎞
0
20log ^d-----^M-----^A----^X------^â‹----V----I--N---
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 15. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F_SW.
Linear Regulator Compensation
DISCUSSION
The linear regulator controller controls an external pass
element, typically a PNP bipolar junction transistor; see
Figure 16 for reference. The error amplifier in the ISL6442
has approximately 72dB (V) of gain. The linear regulator
circuit must be compensated such that the gain of the
internal error amplifier crosses through 0dB with a slope of
20dB/decade. This allows easily predictable phase response
through the 0dB point. The output circuit has a dominant
pole determined by the output capacitance and the
combination of the sense resistor and the output resistance
of the BJT.
F_P1
=
-------------------------¹-------------------------
2π • R_OUT • C_OUT
(EQ. 23)
where:
R_OUT
=
-----------------------¹------------------------
-----------------¹------------------
R301 + R302
+
-¹---
r_o
(EQ. 24)
For most pass elements, r_o is approximately 100kΩ.
It also has a zero determined by the ESR value of the output
capacitor and the Capacitance value of the output capacitor:
F_Z1
=
-------------------------¹-------------------------
2π • R_ESR • C_OUT
(EQ. 25)
The compensation network is composed of R300, C300, the
internal circuitry of the ISL6442, β (also know as h_FE in data
sheets) of the pass element, and the Miller capacitance of
the pass element. The pole is located at:
F_P2
=
----------------¹------------------
2π • R_X • C_X
(EQ. 26)
where:
R_X
=
-----------------------------------¹-------------------------------------
------¹--------
R 300
+
1^----.^--2^---01^----k^---Ω^---
+
3^----2^---0^----1Ω^------•^----β^--
(EQ. 27)
and:
C_X = C300 + 180pF + C_Miller
(EQ. 28)
If C_Miller is unspecified, use 1000pF.
The Zero is located at:
F_Z2
=
-----------------------------¹------------------------------
2π • ESR_C300 • C300
(EQ. 29)
14
FN9204.2
October 31, 2008