ISL6442 Datasheet, PDF (13/16 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6442
C2
COMP
R2 _C1
-
FB
E/A ⁺
VREF
R3 ^C3
R1
Ro
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_IN
L
UGATE
PHASE
LGATE
V_OUT
D
C
E
ISL6442 EXTERNAL CIRCUIT
FIGURE 14. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC
gain, given by d_MAXV_IN/V_OSC, and shaped by the output
filter, with a double pole break frequency at F_LC and a zero at
F_CE. For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
(EQ. 10)
F_CE= ₂----_π-----_â‹--¹-_C------_â‹---_E--
(EQ. 11)
The compensation network consists of the error amplifier
(internal to the ISL6442) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 14. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F₀). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 14, the design procedure can
be followed as presented in Equation 12.
R2 = _d---^V-_M---^O--_A---^S-_X---^C--_â‹---_V^â‹---^R-_I--_N--¹---_â‹--^â‹-_F--^F--_L--⁰-_C---
(EQ. 12)
2. Calculate C1 such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C1
=
-----------------------¹------------------------
2π ⋅ R2 ⋅ 0.5 ⋅ F_LC
(EQ. 13)
3. Calculate C2 such that F_P1 is placed at F_CE.
C2
=
-------------------------^C-----¹---------------------------
2π ⋅ R2 ⋅ C1 ⋅ F_CE – 1
(EQ. 14)
4. Calculate R3 such that F_Z2 is placed at F_LC. Calculate C3
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of F_P2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R3
=
--------^R----¹---------
F_{----S----W----}
F_LC
–
1
C3
=
------------------------¹-------------------------
2π ⋅ R3 ⋅ 0.7 ⋅ F_SW
(EQ. 15)
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
--------------------------¹-----+-----^s----⁽--^f--⁾----^â‹---^E-----^â‹---^C-----------------------------
1 + s(f) ⋅ (E + D) ⋅ C + s²(f) ⋅ L ⋅ C
(EQ. 16)
G_FB(f) = _s----₍-¹-_f---₎-+--_â‹---_Rs----⁽-₁-^f--⁾--_â‹--^â‹-₍--^RC----²-₁----^â‹-+--^C---_C--¹--₂-----₎ ⋅
⋅ -------------------------------¹-----+-----^s---⁽--^f---⁾---^â‹---⁽---^R----¹-----+-----^R-----³----⁾---^â‹---^C-----³-------------------------------- ^{(EQ. 17)}
(
1
+
s
(
f
)
⋅
R3
⋅
C
3)
⋅
⎝⎛ ¹
+
s(f)
⋅
R
2
⋅
⎛
⎝
C^-C----1^{-1----+-⋅---C-}C^----2-2^{--⎠⎞⎠⎞}
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where:
s(f) = 2π ⋅ f ⋅ j
(EQ. 18)
13
FN9204.2
October 31, 2008