ISL6420B Datasheet, PDF (15/20 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420B
SS/EN
C_SS
ISL6420B
GND
BOOT
D1
C_BOOT
PHASE
+5V
VCC
C_VCC
+V_IN
Q1 _LO
V_OUT
Q2 ^CO
FIGURE 15. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
V_IN
ISL6420B
UGATE
PHASE
LGATE
GND
Q1
L_O
V_OUT
Q2 D2
C_IN
C_O
RETURN
FIGURE 16. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Feedback Compensation
Figure 17 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L_O and C_O).
The modulator transfer function is the small-signal transfer
function of Vout/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ΔV_OSC.
OSC
V_IN
DRIVER
PWM
COMPARATOR
L_O
ΔV_OSC
-
DRIVER
+
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
PHASE
C_O
ESR
(PARASITIC)
V_OUT
DETAILED COMPENSATION COMPONENTS
C2
C1
R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
FB
-
+
R₄
ISL6420B
REF
V_OUT
=
V_REF
×
⎛
⎜1
⎝
+
R-R----^14- _{⎠⎟⎞}
FIGURE 17. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
------------------¹--------------------
2π • L_O • C_O
(EQ. 4)
F_ESR=
----------------------¹----------------------
2π • (ESR • C_O)
(EQ. 5)
The compensation network consists of the error amplifier
(internal to the ISL6420B) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180°. The following equations relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 17. Use the following
guidelines for locating the poles and zeros of the
compensation network.
15
FN6901.0
April 27, 2009