ISL6420B Datasheet, PDF (11/20 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420B
TABLE 2. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
PIN CONFIGURATIONS
FUNCTION/MODES
VMSET/MODE
REFOUT
GPIO1/REFIN
(Note 9)
GPIO2
(Note 9)
Enable Voltage Margining
Pin Connected to GND Connect a 2.2µF capacitor Serves as a general
with resistor. It is used for bypass of external
purpose I/O. Refer to
as VMSET.
reference.
Table 3.
Serves as a general
purpose I/O. Refer to
Table 3.
No Voltage Margining. Normal operation
H
Connect a 2.2µF capacitor
H (Note 10)
L
with internal reference. Buffered
to GND.
V_REFOUT = 0.6V.
No Voltage Margining. External
H
Connect a 2.2µF capacitor Connect to an external
L
reference. Buffered V_REFOUT = V_REFIN
to GND.
reference voltage source
(0.6V to 1.25V)
NOTES:
9. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
10. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
GPIO1/REFIN
This is a dual function pin. If VMSET/MODE is not connected
to VCC5 then this pin serves as GPIO1. Refer to Table 3 for
GPIO commands interpretation.
If VMSET/MODE is connected to VCC5 then this pin will
serve as REFIN. As REFIN, this pin is the non-inverting input
to the error amplifier. Connect the desired reference voltage
to this pin in the range of 0.6V to 1.25V.
Connect this pin to VCC5 to use internal reference.
REFOUT
It provides buffered reference output for REFIN. Connect
2.2µF decoupling capacitor to this pin.
VMSET/MODE
This pin is a dual function pin. Tie this pin to VCC5 to disable
voltage margining. When not tied to VCC5, this pin serves as
VMSET. Connect a resistor from this pin to ground to set
delta for voltage margining. If voltage margining and external
reference tracking mode are not needed, this pin can be tied
directly to ground.
GPIO2
This is general purpose IO pin for voltage margining. Refer
to Table 3.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to the
signal ground plane using at least five vias for a robust
thermal conduction path.
TABLE 3. VOLTAGE MARGINING CONTROLLED BY GPIO1
AND GPIO2
GPIO1
GPIO2
VOUT
L
L
No Change
L
H
+ΔVOUT
H
L
-ΔVOUT
H
H
Ignored
Functional Description
Initialization
The ISL6420B automatically initializes upon receipt of power.
The Power-On Reset (POR) function monitors the internal bias
voltage generated from LDO output (VCC5) and the ENSS pin.
The POR function initiates the soft-start operation after the
VCC5 exceeds the POR threshold. The POR function inhibits
operation with the chip disabled (ENSS pin <1V).
The device can operate from an input supply voltage of 5.6V
to 28V connected directly to the VIN pin using the internal 5V
linear regulator to bias the chip and supply the gate drivers.
For 5V ±10% applications, connect VIN to VCC5 to bypass
the linear regulator.
Soft-Start/Enable
The ISL6420B soft-start function uses an internal current
source and an external capacitor to reduce stresses and
surge current during start-up.
When the output of the internal linear regulator reaches the
POR threshold, the POR function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor on the ENSS pin linearly from 0V to 3.3V.
When the ENSS pin voltage reaches 1V typically, the
internal 0.6V reference begins to charge following the dv/dt
of the ENSS voltage. As the soft-start pin charges from 1V to
1.6V, the reference voltage charges from 0V to 0.6V.
Figure 9 shows a typical soft-start sequence.
11
FN6901.0
April 27, 2009