ISL6420B Datasheet, PDF (13/20 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420B
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
150 175 200 225 250 275 300 325 350 375 400
RVMSET (kΩ)
FIGURE 11. VOLTAGE MARGINING vs VMSET RESISTANCE
V_IN = 12V, V_OUT = 3.3V, NO LOAD
FIGURE 12A.
V_IN = 12V, V_OUT = 3.3V, NO LOAD
FIGURE 12B.
V_IN = 12V, V_OUT = 3.3V, I_OUT = 10A
FIGURE 13. PGOOD DELAY
The slew time of the current is set by an external capacitor on
the CDEL pin, which is charged and discharged with a 100µA
current source. The change in voltage on the capacitor is 2.5V.
This same capacitor is used to set the PGOOD active delay
after soft-start. When PGOOD is low, the internal PGOOD
circuitry uses the capacitor and when PGOOD is high, the
voltage margining circuit uses the capacitor. The slew time for
voltage margining can be in the range of 300µs to 2ms.
External Reference/DDR Supply
The voltage margining can be disabled by connecting the
VMSET/MODE to VCC5. In this mode, the chip can be
configured to work with an external reference input and
provide a buffered reference output.
If the VMSET/MODE pin and the GPIO1/REFIN pin are both
tied to VCC5, then the internal 0.6V reference is used as the
error amplifier non-inverting input. The buffered reference
output on REFOUT will be 0.6V ±0.01V, capable of sourcing
20mA and sinking up to 50µA current with a 2.2µF capacitor
connected to the REFOUT pin.
If the VMSET/MODE pin is tied to high but GPIO1/REFIN is
connected to an external voltage source between 0.6V to
1.25V, then this external voltage is used as the reference
voltage at the positive input of the error amplifier. The
buffered reference output on REFOUT will be Vrefin ±0.01V,
capable of sourcing 20mA and sinking up to 50µA current
with a 2.2µF capacitor on the REFOUT pin.
Power-Good
The PGOOD pin can be used to monitor the status of the
output voltage. PGOOD will be true (open drain) when the
FB pin is within ±10% of the reference and the ENSS pin has
completed its soft-start ramp.
Additionally, a capacitor on the CDEL pin will set a delay for the
PGOOD signal. After the ENSS pin completes its soft-start
ramp, a 2µA current begins charging the CDEL capacitor to
2.5V. The capacitor will be quickly discharged before PGOOD
goes high. The programmable delay can be used to sequence
multiple converters or as a LOW-true reset signal.
13
FN6901.0
April 27, 2009