ISL6420B Datasheet, PDF (14/20 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420B
If the voltage on the FB pin exceeds ±10% of the reference,
then PGOOD will go low after 1µs of noise filtering.
Over-Temperature Protection
The IC is protected against over-temperature conditions.
When the junction temperature exceeds +150°C, the PWM
shuts off. Normal operation is resumed when the junction
temperature is cooled down to +130°C.
Shutdown
When ENSS pin is below 1V, the regulator is disabled with
the PWM output drivers tri-stated. When disabled, the IC
power will be reduced.
Undervoltage
If the voltage on the FB pin is less than 15% of the reference
voltage for 8 consecutive PWM cycles, then the circuit enters
into soft-start hiccup mode. This mode is identical to the
overcurrent hiccup mode.
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage by
15%, the lower gate driver is turned on continuously to
discharge the output voltage. If the overvoltage condition
continues for 32 consecutive PWM cycles, then the chip is
turned off with the gate drivers tri-stated. The voltage on the
FB pin will fall and reach the 15% undervoltage threshold.
After 8 clock cycles, the chip will enter soft-start hiccup mode.
This mode is identical to the overcurrent hiccup mode.
Gate Control Logic
The gate control logic translates generated PWM control
signals into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operational conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control logic
provides adaptive dead time by monitoring the gate-to-
source voltages of both upper and lower MOSFETs. The
lower MOSFET is not turned on until the gate-to-source
voltage of the upper MOSFET has decreased to less than
approximately 1V. Similarly, the upper MOSFET is not turned
on until the gate-to-source voltage of the lower MOSFET has
decreased to less than approximately 1V. This allows a wide
variety of upper and lower MOSFETs to be used without a
concern for simultaneous conduction, or shoot-through.
Startup into Pre-Biased Load
The ISL6420B is designed to power-up into a pre-biased
load. This is achieved by transitioning from Diode Emulation
mode to a Forced Continuous Conduction mode during
startup. The lower gate turns ON for a short period of time
and the voltage on the phase pin is sensed. When this goes
negative the lower gate is turned OFF and remains OFF till
the next cycle. As a result, the inductor current will not go
negative during soft-start and thus will not discharge the
pre-biased load. The waveform for this condition is shown in
Figure 14.
V_IN = 12V, V_OUT = 3.3V at 25mA LOAD
FIGURE 14. PREBIASED OUTPUT AT 25mA LOAD
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
Figure 16 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 16 should be located as close
together as possible. Please note that the capacitors C_IN
and C_O each represent numerous physical capacitors.
Locate the ISL6420B within 3 inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the ISL6420B must be sized to
handle up to 1A peak current.
Figure 15 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C_ss
close to the SS pin because the internal current source is
only 10µA. Provide local V_CC decoupling between VCC and
GND pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins.
14
FN6901.0
April 27, 2009