ISL6420 Datasheet, PDF (15/19 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420
OSC
V_IN
DRIVER
PWM
COMPARATOR
L_O
∆V_OSC
-
+
DRIVER
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
PHASE
C_O
ESR
(PARASITIC)
V_OUT
DETAILED COMPENSATION COMPONENTS
C2
C1
R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
ISL6420
FB
-
+
REF
FIGURE 14. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Feedback Compensation
Figure 14 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L_O and C_O).
The modulator transfer function is the small-signal transfer
function of Vout/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage DV_OSC.
Modulator Break Frequency Equations
F_LC=
------------------¹--------------------
2π • L_O • C_O
(EQ. 4)
F_ESR=
----------------------¹----------------------
2π • (ESR • C_O)
(EQ. 5)
The compensation network consists of the error amplifier
(internal to the ISL6420) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180^o. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 14. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F_Z1
=
----------------¹------------------
2π • R2 • C1
(EQ. 6)
F_P1
=
--------------------------¹----------------------------
2
π
•
R
2
•


C^-C----1^{-1----+•-----CC----2-}2^{--}
(EQ. 7)
F_Z2 = ₂----_π-----_•----₍---_R-----₁----+-¹----_R-----₃----₎---_•-----_C----₃--
(EQ. 8)
F_P2
=
----------------¹------------------
2π • R3 • C3
(EQ. 9)
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole
(~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 15 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak do to the high Q factor of the output
filter and is not shown in Figure 15. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 15 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
15
FN9151.4
July 18, 2005