ISL6420 Datasheet, PDF (12/19 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420
Functional Description
Initialization
The ISL6420 automatically initializes upon receipt of power.
The Power-On Reset (POR) function monitors the internal
bias voltage generated from LDO output (VCC5) and the
ENSS pin. The POR function initiates the soft-start operation
after the VCC5 exceeds the POR threshold. The POR
function inhibits operation with the chip disabled (ENSS
pin <1V).
The device can operate from an input supply voltage of 5.6V
to 16V connected directly to the VIN pin using the internal 5V
linear regulator to bias the chip and supply the gate drivers.
For 5V ±10% applications, connect VIN to VCC5 to bypass
the linear regulator.
Soft-Start/Enable
The ISL6420 soft-start function uses an internal current
source and an external capacitor to reduce stresses and
surge current during startup.
When the output of the internal linear regulator reaches the
POR threshold, the POR function initiates the soft-start
sequence. An internal 10µA current source charges an
external capacitor on the ENSS pin linearly from 0V to 3.3V.
When the ENSS pin voltage reaches 1V typically, the
internal 0.6V reference begins to charge following the dv/dt
of the ENSS voltage. As the soft-start pin charges from 1V to
1.6V, the reference voltage charges from 0V to 0.6V.
Figure 8 shows a typical soft-start sequence.
FIGURE 8. TYPICAL SOFT-START WAVEFORM
Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r_DS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor connected
to the drain of the upper FET and the OCSET pin programs
the overcurrent trip level. The PHASE node voltage will be
compared against the voltage on the OCSET pin, while the
upper FET is on. A current (100µA typically) is pulled from
the OCSET pin to establish the OCSET voltage. If PHASE is
lower than OCSET while the upper FET is on then an
overcurrent condition is detected for that clock cycle. The
upper gate pulse is immediately terminated, and a counter is
incremented. If an overcurrent condition is detected for
8 consecutive clock cycles, and the circuit is not in soft-start,
the ISL6420 enters into the soft-start hiccup mode. During
hiccup, the external capacitor on the ENSS pin is
discharged. After the cap is discharged, it is released and a
soft-start cycle is initiated. During soft-start, pulse
termination current limiting is enabled, but the 8-cycle hiccup
counter is held in reset until soft-start is completed.
The overcurrent function will trip at a peak inductor current
(I_OC) determined from Equation 1, where I_OCSET is the
internal OCSET current source.
The OC trip point varies mainly due to the upper MOSFETs
r_DS(ON) variations. To avoid overcurrent tripping in the
normal operating load range, find the R_OCSET resistor from
the equation above with:
1. The maximum r_DS(ON) at the highest junction
temperature.
2. Determine I_OC for I_OC > I_OUT(MAX) + (∆I) ⁄ 2 ,
where ∆I is the output inductor ripple current.
A small ceramic capacitor should be placed in parallel with
R_OCSET to smooth the voltage across R_OCSET in the
presence of switching noise on the input voltage.
Voltage Margining
The ISL6420 has a voltage margining mode that can be
used for system testing. The voltage margining percentage
is resistor selectable up to ±10%. The voltage margining
mode can be enabled by connecting a margining set resistor
from VMSET/MODE pin to ground and using the control pins
GPIO1/REFIN and GPIO2 to toggle between positive and
negative margining (Refer to Table 2). With voltage
margining enabled, the VMSET resistor to ground sets a
current, which is switched to the FB pin. The current will be
equal to 2.468V divided by the value of the external resistor
tied to the VMSET/MODE pin.
I_VM
=
---²---^.--⁴---⁶----⁸---^V-----
R_VMSET
(EQ. 2)
∆V_VM
=
2.468 V
-------^R----^F----^B--------
R_VMSET
(EQ. 3)
The power supply output increases when GPIO2 is HIGH
and decreases when GPIO1/REFIN is HIGH. The amount
12
FN9151.4
July 18, 2005