ISL6420 Datasheet, PDF (11/19 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6420
VMSET/MODE - This pin is a dual function pin. Tie this pin to
VCC5 to disable voltage margining. When not tied to VCC5,
this pin serves as VMSET. Connect a resistor from this pin to
ground to set the delta for voltage margining. If voltage
margining and external reference tracking mode are not
needed, this pin can be tied directly to ground.
GPIO2 - This is general purpose IO pin for voltage
margining. Refer to Table 2.
TABLE 2. VOLTAGE MARGINING CONTROLLED BY
GPIO1/REFIN AND GPIO2
GPIO1/REFIN
GPIO2
VOUT
L
L
No Change
L
H
+ Delta VOUT
H
L
- Delta VOUT
H
H
Ignored
TABLE 3. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
PIN CONFIGURATIONS
FUNCTION/MODES
VMSET/MODE
REFOUT
GPIO1/REFIN
GPIO2
COMMENTS
Enable Voltage
Margining
Pin Connected to GND Connect a 1µF
Serves as a general
with resistor. It is used capacitor for bypass of purpose I/O. Refer to
as VMSET.
external reference. Table 2
Serves as a general
purpose I/O. Refer to
Table 2
REFIN or REFOUT
functions will not be
available in this mode.
The internal 0.6V
reference is used.
No Voltage Margining. Pin Connected to GND Connect a 1µF
L
L
Normal operation using with resistor. It is used capacitor for bypass of
internal reference.
as VMSET
external reference.
REFOUT not used.
No Voltage Margining.
H
Connect a 2.2µF
H (Note 2)
L
Normal operation with
capacitor to GND.
internal reference.
Buffered V_REFOUT =
0.6V.
No Voltage Margining.
H
Connect a 2.2µF
Connect to an external
L
External reference.
capacitor to GND.
reference voltage
Buffered V_REFOUT =
V_REFIN
source (0.6V to 1.25V)
NOTES:
1. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
2. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
11
FN9151.4
July 18, 2005