ISL6523 Datasheet, PDF (14/16 Pages) Intersil Corporation – VRM8.5 Dual PWM and Dual Linear Power System Controller

ISL6523
+12V
VCC
ISL6523
UGATE
PHASE
-
LGATE
+
PGND
GND
+5V OR LESS
Q1
NOTE:
V_GS ≈ V_CC -5V
Q2
CR1
NOTE:
V_GS ≈ V_CC
FIGURE 12. UPPER GATE DRIVE - DIRECT V_CC DRIVE
The power dissipation in PWM2 converter is similar to
PWM1 except that the power losses of the lower device are
dissipated in the Schottky. The equations below describe an
approximation of this power loss distribution and assume
linear voltage-current switching transitions.
P_MOS
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----V_{----O-----U----T-- + -}I_-O------×_-----V_{----I--N-----}×_-----t_{--S----W------}×_-----F_----S--
V_IN
2
P_SCH
=
I_--O------×_-----V_----f---×_-----(_--V_{----I--N------–----}V_{----O-----U----T----})
V_IN
Linear Controllers Transistor Selection
The ISL6523 linear controllers are compatible with both NPN
bipolar as well as N-channel MOSFET transistors. The main
criteria for selection of pass transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is
P_LINEAR = I_O × (V_IN – V_OUT)
Select a package and heatsink that maintains the junction
temperature below the maximum desired temperature with
the maximum expected ambient temperature.
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating V_CE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.
In order to ensure the strict timing/level requirement of
OUT4, an NPN transistor is recommended for use as a pass
element on this output (Q5). An low gate threshold NMOS
could be used, but meeting the requirements would then
depend on the VCC bias being sufficiently high to allow
control of the MOSFET.
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