ISL6523 Datasheet, PDF (11/16 Pages) Intersil Corporation – VRM8.5 Dual PWM and Dual Linear Power System Controller

ISL6523
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT) for
PWM1. The error amplifier output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V_IN at the PHASE node.
The PWM wave is smoothed by the output filter (L_O and C_O)..
V_IN
OSC
DRIVER
∆V_OSC
PWM
COMP
-
+
DRIVER
L_O
V_OUT
PHASE
C_O
V_E/A
Z_FB
-
+
ERROR
AMP
Z_IN
REFERENCE
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
FB
-
+
ISL6523
DACOUT
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain, given by V_IN/V_OSC, and shaped by the output filter, with
a double pole break frequency at F_LC and a zero at F_ESR.
Modulator Break Frequency Equations
F_LC=
-------------------¹--------------------
2π × L_O × C_O
F_ESR=
--------------------¹---------------------
2π × ESR × C_O
The compensation network consists of the error amplifier
(internal to the ISL6523) and the impedance networks Z_IN and
Z_FB. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f_0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f_0dB and 180^o.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^STZero Below Filter’s Double Pole (~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
F_Z1 = ₂----_π-----_×-----_R---¹--₂-----_×----_C-----₁--
F_P1
=
---------------------------¹---------------------------
2
π
×
R₂
×


C^-C----11^{-----+×-----CC-----22--}
F_Z2
=
---------------------------¹---------------------------
2π × (R1 + R3) × C3
F_P2
=
-----------------¹------------------
2π × R3 × C3
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
100
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
ERROR AMP GAIN
80
20 log



V^----V-_P^{----I-–-N----}_P^--_{}
60
40
COMPENSATION
GAIN
20
0
-20
20
log


RR_-----21_{--}
MODULATOR
-40
GAIN
F_LC F_ESR
CLOSED LOOP
GAIN
-60
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
11