ISL267440_14 Datasheet, PDF (14/18 Pages) Intersil Corporation – 10-Bit and 12-Bit, 1MSPS SAR ADCs

ISL267440, ISL267450A
FIGURE 29. ISL267450A SYSTEM TIMING
FIGURE 30. ISL267440 SYSTEM TIMING
Power vs Throughput Rate
The ISL267440 and ISL267450A provide reduced power
consumption at lower conversion rates by automatically
switching into a low-power mode after completing a conversion.
The average power consumption of the ADC decreases at lower
throughput rates. Figure 31 shows the typical power
consumption over a wide range of throughput rates.
100
10
V_DD = 5V
1
Serial Digital Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
The serial interface is designed around using 16 SCLK cycles to
perform an autozero on the SAR comparator and additional SCLK
cycles for SAR comparator decisions (12 SLCKs in the 12-bit
device, 10 SCLKs in the 10-bit device, and 8 SCLKs in the 8-bit
device). If short cycling is not used, all converter throughput
cycles take 16 SCLKs. The SDATA output goes low after the last
conversion decision has been presented to the SDATA output, as
shown in Figures 29 and 30.
0.1
V_DD = 3V
0.01
0
50
100 150 200 250 300 350
THROUGHPUT (Ksps)
FIGURE 31. POWER CONSUMPTION vs THROUGHPUT RATE
14
FN7708.2
June 28, 2012