ISL267440_14 Datasheet, PDF (13/18 Pages) Intersil Corporation – 10-Bit and 12-Bit, 1MSPS SAR ADCs

ISL267440, ISL267450A
5V
0.1µF
+ ^BULK
1 DNC DNC 8
2 V_IN
DNC 7
3 COMP V_OUT 6
4 GND TRIM 5
2.5V
ISL21090
ISL267440 ^VDD
ISL267450A
VREF
0.1µF
0.1µF
FIGURE 27. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+2.7V TO +3.6V
OR +5V
V_IN 1
V_OUT 2
GND
3
ISL21010
+
BULK
0.1µF
ISL267440 ^VDD
ISL267450A
VREF
1.25, 2.048 OR 2.5V
0.1µF
0.1µF
FIGURE 28. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
The ISL267440 and ISL267450A are designed to minimize
power consumption by only powering up the SAR comparator
during conversion time. When the converter is in track mode (its
sample capacitors are tracking the input signal) the SAR
comparator is powered down. The state of the converter is
dictated by the logic state of CS. When CS is high, the SAR
comparator is powered down while the sampling capacitor array
is tracking the input. When CS transitions low, the capacitor array
immediately captures the analog signal that is being tracked.
After CS is taken low, the SCLK pin is toggled 16 times. For the
first 3 clocks, the comparator is powered up and auto-zeroed,
then the SAR decision process is begun. This process uses 12
SCLK cycles for the 12-bit ISL267450A. Each SAR decision is
presented to the SDATA output on the next clock cycle after the
SAR decision is performed. The SAR process (12 bits) is
completed on SCLK cycle 15. At this point in time, the SAR
comparator is powered down and the capacitor array is placed
back into Track mode. The last SAR comparator decision is
output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
Figures 29 and 30 on page 14 illustrate the system timing for the
12, and 10-bit converters respectively.
Power-On Reset
When power is first applied, the ISL267440/ISL267450A
performs a power-on reset that requires approximately 2.5ms to
execute. After this is complete, a single dummy conversion must
be executed (by taking CS low) in order to initialize the switched
capacitor track and hold. The dummy conversion cycle will take
1µs with an 18MHz SCLK. Once the dummy cycle is complete,
the ADC mode will be determined by the state of CS. Regular
conversions can be started immediately after this dummy cycle
is completed and time has been allowed for proper acquisition.
Acquisition Time
To achieve the maximum sample rate (1MSps) in the
ISL267450A device, the maximum acquisition time is 200ns. For
slower conversion rates, or for conversions performed using a
slower SCLK value than 18MHz, the minimum acquisition time is
200ns. This same minimum applies to the ISL267440. This
minimum acquisition time also applies to all the devices if short
cycling is utilized.
Short Cycling
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all SCLK falling edges have elapsed.
This is referred to as short cycling, and it can be used to further
optimize power dissipation. In this mode, a lower resolution
result will be output, but the ADC will enter static mode sooner
and exhibit a lower average power consumption than if the
complete conversion cycle were carried out. The minimum
acquisition time (t_ACQ) requirement of 200ns must be met for
the next conversion to be valid.
13
FN7708.2
June 28, 2012