ISL22444 Datasheet, PDF (14/19 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometer XDCP

ISL22444
CS
SCK
SDI
SDO
1
8
RD
ADDR
16
24
32
NOP
RD
ADDR
READ DATA
FIGURE 17. FOUR BYTE READ SEQUENCE
Applications Information
Communicating with ISL22444
Communication with ISL22444 proceeds using SPI interface
through the ACR (address 10000b), IVRi (address 00000b,
00001b, 00010b or 00011b), WRi (addresses 00000b,
00001b, 00010b or 00011b) and General Purpose registers
(addresses from 00100b to 01110b).
The wiper position of each potentiometer is controlled by the
corresponding WRi register. Writes and reads can be made
directly to these registers to control and monitor the wiper
position without any non-volatile memory changes. This is
done by setting MSB bit at address 10000b to 1 (ACR[7] = 1).
The non-volatile IVRi stores the power up position of the
wiper. IVRi is accessible when MSB bit at address 10000b is
set to 0 (ACR[7] = 0). Writing a new value to the IVRi register
will set a new power up position for the wiper. Also, writing to
this register will load the same value into the corresponding
WRi as the IVRi. Reading from the IVRi will not change the
WRi, if its contents are different.
Daisy Chain Configuration
When application needs more then one ISL22444, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs as shown on Figure 18. In Daisy
Chain configuration the SDO pin of previous chip is
connected to SDI pin of the following chip, and each CS and
SCK pins are connected to the corresponding
microcontroller pins in parallel, like regular SPI interface
implementation. The Daisy Chain configuration can also be
used for simultaneous setting of multiple DCPs. Note, the
number of daisy chained DCPs is limited only by the driving
capabilities of SCK and CS pins of microcontroller; for larger
number of SPI devices buffering of SCK and CS lines is
required.
Daisy Chain Write Operation
The write operation starts by HIGH to LOW transition on CS
line, followed by N two bytes write instructions on SDI line
with reversed chain access sequence: the instruction byte +
data byte for the last DCP in chain is going first, as shown on
Figure 19. The serial data is going through DCPs from DCP0
to DCP(N-1) as follows: DCP0 --> DCP1 --> DCP2 --> ... -->
DCP(N-1). The write instruction is executed on the rising
edge of CS for all N DCPs simultaneously.
Daisy Chain Read Operation
The read operation consists of two parts: first, send read
instructions (N two bytes operation) with valid address;
second, read the requested data while sending NOP
instructions (N two bytes operation) as shown on Figure 20
and Figure 21.
The first part starts by HIGH to LOW transition on CS line,
followed by N two bytes read instruction on SDI line with
reversed chain access sequence: the instruction byte +
dummy data byte for the last DCP in chain is going first,
followed by LOW to HIGH transition on CS line. The read
instructions are executed during second part of read
sequence. It also starts by HIGH to LOW transition on CS
line, followed by N two bytes NOP instructions on SDI line
and LOW to HIGH transition of CS. The data is read on
every even byte during second part of read sequence while
every odd byte contains instruction code + address from
which the data is being read.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the
sudden transition from a very low impedance “make” to a
much higher impedance “break within an extremely short
period of time (<50ns). Two such code transitions are EFh to
F0h, and 0Fh to 10h. Note, that all switching transients will
settle well within the settling time as stated on the datasheet.
A small capacitor can be added externally to reduce the
amplitude of these voltage transients, but that will also
reduce the useful bandwidth of the circuit, thus may not be a
good solution for some applications. It may be a good idea,
in that case, to use fast amplifiers in a signal chain for fast
recovery.
14
FN6426.0
May 24, 2007