ISL22444 Datasheet, PDF (11/19 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometer XDCP

ISL22444
Typical Performance Curves (Continued)
CS
SCL
WIPER
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
Pin Description
Potentiometer Pins
RHI AND RLI
The high (RHi) and low (RLi) terminals of the ISL22444 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.
RWI
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL CLOCK (SCK)
This is the serial clock input of the SPI serial interface.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the
data bits are shifted out on the falling edge of the serial clock
SCK and will be available to the master on the following
rising edge of SCK.
The output type is configured through ACR[1] bit for Push-
Pull or Open Drain operation. Default setting for this pin is
Push-Pull. An external pull up resistor is required for Open
Drain output operation. Note: the external pull up voltage not
allowed beyond V_CC.
SERIAL DATA INPUT (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI remote host device. The data bits are
11
FIGURE 14. LARGE SIGNAL SETTLING TIME
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
CHIP SELECT (CS)
CS LOW enables the ISL22444, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22444 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
The ISL22444 is an integrated circuit incorporating four
DCPs with their associated registers, non-volatile memory
and the SPI serial interface providing direct communication
between host, potentiometers and memory. The resistor
arrays are comprised of individual resistors connected in a
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the content of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial position.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
FN6426.0
May 24, 2007