ISL22444 Datasheet, PDF (13/19 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometer XDCP

ISL22444
on the falling edge of SCK. CS must be LOW during
communication with the ISL22444. SCK and CS lines are
controlled by the host or master. The ISL22444 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one
or more Data Bytes. A valid Instruction Byte contains
instruction as the three MSBs, with the following five register
address bits (see Table 3).
The next byte sent to the ISL22444 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
BIT # 7
6
5
4
3
2
1
0
I2 I1 I0 R4 R3 R2 R1 R0
Table 4 contains a valid instruction set for ISL22444.
There are only sixteen register addresses possible for this
DCP. If the [R4:R0] bits are 00000, 00001, 00010 or 00011
then the read or write is to either the IVRi or the WRi
registers (depends of VOL bit at ACR). If the [R4:R0] are
10000, then the operation is on the ACR.
Write Operation
A Write operation to the ISL22444 is a two or more bytes
operation. First, It requires, the CS transition from HIGH to
LOW. Then host must send a valid Instruction Byte followed
by one or more Data Bytes to SDI pin. The host terminates
the write operation by pulling the CS pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write-to
address 00h, 01h, 02h or 03h, the MSB of the byte at
address 10h (ACR[7]) determines if the Data Byte is to be
written to volatile or both volatile and non-volatile registers.
Refer to “Memory Description” and Figure 16. Note: the
internal non-volatile write cycle starts with the rising edge of
CS and requires up to 20ms. During non-volatile write cycle
the read operation to ACR register is allowed to check WIP
bit.
Read Operation
A Read operation to the ISL22444 is a four byte operation. It
requires first, the CS transition from HIGH to LOW. Then the
host must send a valid Instruction Byte followed by “dummy”
Data Byte, a NOP Instruction Byte and another “dummy”
Data Byte to SDI pin. The SPI host receives the Instruction
Byte (instruction code + register address) and requested
Data Byte from SDO pin on rising edge of SCK during third
and fourth bytes respectively. The host terminates the read
operation by pulling the CS pin from LOW to HIGH (see
Figure 17). Reading from the IVRi will not change the WRi, if
its contents are different.
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
I2
I1
I0
R4
R3
R2
R1
R0
OPERATION
0
0
0
X
X
X
X
X NOP
0
0
1
X
X
X
X
X ACR READ
0
1
1
X
X
X
X
X ACR WRITE
1
0
0
R4
R3
R2
R1
R0 WR, IVR, GP or ACR READ
1
1
0
R4
R3
R2
R1
R0 WR, IVR, GP or ACR WRITE
where X means “do not care”.
CS
SCK
SDI
SDO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
WR INSTRUCTION
ADDR
DATA BYTE
FIGURE 16. TWO BYTE WRITE SEQUENCE
13
FN6426.0
May 24, 2007