ISL6334AR5368 Datasheet, PDF (13/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

ISL6334AR5368
.
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
IL2, 7A/DIV
IL3, 7A/DIV
PWM2, 5V/DIV
PWM3, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine Equation 1, which represents an
individual channel’s peak-to-peak inductor current.
I_{PP =}
(_{---V----I--N-----}–_{-----V----O-----U----T---})_{----V----O----U-----T-}
L F_SW V_IN
(EQ. 1)
In Equation 1, V_IN and V_OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and F_SW is the switching frequency.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
I_{C, PP}=
(_{---V----I--N-----}–_{-----N------V----O-----U----T---})_{----V----O----U-----T-}
L
f_S
V
I
N
(EQ. 2)
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A_RMS
input capacitor current. The single-phase converter must use
an input capacitor bank with twice the RMS current capacity as
the equivalent three-phase converter.
Figures 18, 19 and 20 in the section entitled “Input Capacitor
Selection” on page 28 can be used to determine the input
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provided as aids in
determining the optimal input capacitor solution. Figure 21
shows the single phase input-capacitor RMS current for
comparison.
PWM Modulation Scheme
The ISL6334AR5368 adopts Intersil's proprietary Active
Pulse Positioning (APP) modulation scheme to improve
transient performance. APP control is a unique dual-edge
PWM modulation scheme with both PWM leading and
trailing edges being independently moved to give the best
response to transient loads. The PWM frequency, however,
is constant and set by the external resistor between the FS
pin and GND. To further improve the transient response, the
ISL6334AR5368 also implements Intersil's proprietary
Adaptive Phase Alignment (APA) technique. APA, with
sufficiently large load step currents, can turn on all phases
together. With both APP and APA control, ISL6334AR5368
can achieve excellent transient performance and reduce
demand on the output capacitors.
Under steady state conditions, the operation of the
ISL6334AR5368 PWM modulators appear to be that of a
conventional trailing edge modulator. Conventional analysis
and design methods can therefore be used for steady state
and small signal operation.
PWM and PSI# Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the
ISL6334AR5368 is four. The switching cycle is defined as
the time between PWM pulse termination signals of each
channel. The cycle time of the pulse signal is the inverse of
the switching frequency set by the resistor between the FS
13
FN6839.2
September 7, 2010