ISL6554 Datasheet, PDF (12/16 Pages) Intersil Corporation – Microprocessor CORE Voltage Regulator Using Multi-Phase Buck PWM Control Without Programmable Droop

ISL6554
25
20
15
10
5
0
FIGURE 8. TWO CHANNEL MULTI-PHASE SYSTEM WITH
CURRENT BALANCING DISABLED
25
20
15
10
5
0
FIGURE 9. TWO CHANNEL MULTI-PHASE SYSTEM WITH
CURRENT BALANCING ENABLED
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is r_DSON
(Q2) x I_SAMPLE. The voltage at Q2’s drain, the PHASE node,
is applied through the R_ISEN resistor to the ISL6554 ISEN pin.
This pin is held at virtual ground, so the current into ISEN is:
I_SENSE
= I_SAMPLE x r_DS(ON) (Q2) / R_ISEN.
R_Isen
= I_SAMPLE x r_DS(ON) (Q2) / 50µA
Example: From the previous conditions,
where I_LT
I_SAMPLE
r_DS(ON) (Q2)
Then: R_ISEN
I_{CURRENT TRIP}
Short circuit I_LT
= 100A,
= 25.49A,
= 4mΩ
= 2.04K and
= 165%
= 165A.
Channel Frequency Oscillator
The channel oscillator frequency is set by placing a resistor,
R_T, to ground from the FS/DIS pin. Figure 10 is a curve
showing the relationship between frequency, F_SW, and
12
resistor R_T. To avoid pickup by the FS/DIS pin, it is important
to place this resistor next to the pin.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turnoff transition of
the upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current stops
flowing in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. Contact Intersil for evaluation
board drawings of the component placement and printed
circuit board.
There are two sets of critical components in a DC-DC
converter using a ISL6554 controller and a HIP6601 gate
driver. The power components are the most critical because
they switch large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C_IN,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the gate driver close to the MOSFETs.
The critical small components include the bypass capacitors for
VCC and PVCC on the gate driver ICs. Locate the bypass
capacitor, C_BP, for the ISL6554 controller close to the device. It
is especially important to locate the resistors associated with
the input to the amplifiers close to their respective pins, since
they represent the input to feedback amplifiers. Resistor R_T,
that sets the oscillator frequency should also be located next to
the associated pin. It is especially important to place the R_SEN
resistors at the respective terminals of the ISL6554.
A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components for one
output channel of the converter. Note that capacitors C_IN and
C_OUT could each represent numerous physical capacitors.
Dedicate one solid layer, usually the middle layer of the PC
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from
the PHASE terminal to output inductor short. The power plane
should support the input power and output power nodes. Use
FN9003.3
February 11, 2005