ISL6554 Datasheet, PDF (10/16 Pages) Intersil Corporation – Microprocessor CORE Voltage Regulator Using Multi-Phase Buck PWM Control Without Programmable Droop

ISL6554
time. PGOOD also goes “low” during this time due to VSEN
going below its threshold voltage. To lower the average
output dissipation, the soft-start initial wait time is increased
from 32 to 2048 cycles, then the soft-start ramp is initiated.
At a PWM frequency of 200kHz, for instance, an overcurrent
detection would cause a dead time of 10.24ms, then a ramp
of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
soft-start ramp is initiated. If a short is present at that time,
the cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to
the high short circuit current, overcurrent is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal soft-start cycle.
SHORT APPLIED HERE
PGOOD
SHORT
CURRENT
50A/DIV.
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SUPPLY FREQUENCY = 200kHz, V _IN = 12V
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
CORE Voltage Programming
The voltage identification pins (VID0, VID1,VID2,VID3 and
VID4) set the CORE output voltage. Each VID pin is pulled to
VCC by an internal 20µA current source and accepts open-
collector/open-drain/open-switch-to-ground or standard low-
voltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is ±1% accurate over
the operating temperature and voltage range.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID4
VID3 VID2 VID1 VID0
1
1
1
1
1
VCC_CORE
(V_DC)
Output Off
1
1
1
1
0
0.95
1
1
1
0
1
0.975
1
1
1
0
0
1.000
1
1
0
1
1
1.025
1
1
0
1
0
1.050
1
1
0
0
1
1.075
1
1
0
0
0
1.100
1
0
1
1
1
1.125
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID4
VID3 VID2 VID1 VID0
1
0
1
1
0
VCC_CORE
(V_DC)
1.150
1
0
1
0
1
1.175
1
0
1
0
0
1.200
1
0
0
1
1
1.225
1
0
0
1
0
1.250
1
0
0
0
1
1.275
1
0
0
0
0
1.300
0
1
1
1
1
1.325
0
1
1
1
0
1.350
0
1
1
0
1
1.375
0
1
1
0
0
1.400
0
1
0
1
1
1.425
0
1
0
1
0
1.450
0
1
0
0
1
1.475
0
1
0
0
0
1.500
0
0
1
1
1
1.525
0
0
1
1
0
1.550
0
0
1
0
1
1.575
0
0
1
0
0
1.600
0
0
0
1
1
1.625
0
0
0
1
0
1.650
0
0
0
0
1
1.675
0
0
0
0
0
1.700
Current Sensing and Balancing
Overview
The ISL6554 samples the on-state voltage drop across each
synchronous rectifier MOSFET, Q2, as an indication of the
inductor current in that phase (see Figure 7). Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r_DS(ON)(Q2) x inductor current (I_L). Note that I_L, the
inductor current, is either 1/2, 1/3, or 1/4 of the total current
(I_LT), depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
R_ISEN resistor to develop the I_ISEN current to the ISL6554
ISEN pin. This pin is held at virtual ground, so the current
through R_ISEN is I_L x r_DS(ON)(Q2) / R_ISEN.
The I_ISEN current provides information to perform the
following functions:
1. Detection of an overcurrent condition
2. Balance the I_L currents in multiple channels
Overcurrent, Selecting RISEN
The current detected through the R_ISEN resistor is
averaged with the current(s) detected in the other 1, 2, or 3
channels. The averaged current is compared with a
trimmed, internally generated current, and used to detect
an overcurrent condition.
10
FN9003.3
February 11, 2005