ISL6444_07 Datasheet, PDF (12/19 Pages) Intersil Corporation – Dual PWM Controller with DDR Memory Option for Gateway Applications

ISL6444
Overtemperature Protection
The chip incorporates an over temperature protection circuit
that shuts the chip down when the die temperature of
+150°C is reached. Normal operation restores at die
temperatures below +125°C through the full soft-start cycle.
DDR Application
Double Data Rate (DDR) memory chips are expected to take
a place of memory of choice in many newly designed
computers including high-end notebooks due to increased
throughput. A novelty feature associated with this type of
memory is new referencing and data bus termination
techniques. These techniques employ a reference voltage,
VREF, that tracks the center point of VDDQ and VSS
voltages and an additional VTT power source to which all
terminating resistors are connected. Despite the additional
power source, the overall memory power consumption is
reduced compared to traditional termination.
The added power source has a cluster of requirements that
should be observed and considered. Due to reduced
differential thresholds of DDR memory, the termination
power supply voltage, VTT, shall closely track VDDQ/2
voltage. Another very important feature for the termination
power supply is a capability to equally operate in sourcing
and sinking modes. The VTT supply shall regulate the output
voltage with the same degree of precision when current is
floating from the supply to the load and when the current is
diverted back from the load into the power supply. The last
mode of operation usually conflicts with the way most PWM
controllers operate.
The ISL6444 dual channel PWM controller possesses
several important means that allow re configuration for this
particular application and provide all three voltages required
in DDR memory compliant computer.
To reconfigure the ISL6444 for a complete DDR solution, the
DDR pin shall be permanently set high. The simplest way to
do that is to connect it to the VCC rail. This activates some
functions inside the chip that are specific to the DDR
memory power needs.
In DDR application presented in Figure 12, the first controller
regulates VDDQ rail to 2.5V. The output voltage is set by an
external divider R3 and R4. The second controller regulates
the VTT rail to VDDQ/2. The OCSET2 pin function is now
different. The pin serves now as an input that brings VDDQ/2
voltage created by R5 and R6 divider inside the chip. That
effectively provides a tracking function for the VTT voltage.
The PG2 pin function is also different in DDR mode. This pin
becomes the output of the buffer, which input is connected
via the OCSET2 pin to the center point of the R/R divider
from the VDDQ output. The buffer output voltage serves as
1.25V reference for the DDR memory chips. Current
capability of this pin is about 10mA.
For the VTT channel some control and protective functions
can be significantly simplified as this output is derived from
the VDDQ output. For example, the overcurrent and
overvoltage protections for the second controller are
disabled when the DDR pin is set high. The hysteretic mode
of operation is also disabled on the VTT channel to allow
sinking capability to be independent from the load level. As
the VTT channel tracks the VDDQ/2 voltage, the soft-start
function is not required and the SOFT2 pin may be left open
or may be connected to VCC.
Channel Synchronization in DDR
Applications
Presence of two PWM controllers on the same die require
channel synchronization to reduce inter channel interference
that may cause the duty factor jitter and increased output
ripple. The PWM controller is mostly susceptible to noise
when an error signal on the input of the PWM comparator
approaches the decision making point. False triggering can
occur causing jitter and affecting the output regulation.
Out-of-phase operation is a common approach to
synchronize dual channel converters as it reduces an input
current ripple and provides a minimum interference for
channels that control different voltage levels. When used in
DDR application with cascaded converters (VTT generated
from VDDQ), the turn-on of the upper MOSFET in the VDDQ
channel happens to be just before the decision making point
in the VTT channel that is running with a duty-factor close to
50%, Figure 7 and Figure 8. This makes out-of-phase
channel synchronization undesirable when one of the
channels is running on a duty-factor of 50%. Inversely, the
in-phase channel arrangement does not have this drawback.
Points of decision are far from noisy moments of time in both
sourcing and sinking modes of operation for VIN = 7.5V to
24V as it is shown in Figure 7.
12
FN9069.3
April 12, 2007