ISL6444_07 Datasheet, PDF (10/19 Pages) Intersil Corporation – Dual PWM Controller with DDR Memory Option for Gateway Applications

ISL6444
is usually higher compared to the load level at which
transition into hysteretic mode had occurred.
VOUT pin and Forced Continuous Conduction Mode (FCCM)
The error amplifier that provides control over the converter
during CCM mode is excluded from the regulation loop in the
hysteretic mode. Due to that, its output voltage eventually
runs away from the operation point that is normally related to
the desired output voltage. When the converter transitions
from hysteretic mode of operation into CCM, the output
voltage transient can occur as it takes some time for the
error amplifier to catch-up with regulation.
To reduce undesirable effects of the error amplifier run away
during mode change, the exact value of the output voltage is
provided to the internal circuit via the VOUT pin, Figure 2.
In case the hysteretic mode of operation is not required, the
controller can be put in a forced continuous conduction
mode (FCCM) of operation. That can be accomplished by
connecting the VOUT pin to ground, which disables the
mode control circuit.
Such dual function of the VOUT pin enhances applicability of
the controller and allows for lower pin count.
Feedback Loop Compensation
To reduce the number of external components and remove
the burden of determining compensation components from a
system designer, both PWM controllers have internally
compensated error amplifiers. To make internal compensation
possible several design measures where taken.
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant when the input
voltage varies. The second, the load current proportional
signal is derived from the voltage drop across the lower
MOSFET during the PWM time interval and is added to the
amplified error signal on the comparator input. This
effectively creates an internal current control loop. The
resistor connected to the ISEN pin sets the gain in the
current feedback loop. Equation 6 estimates the required
value of the current sense resistor depending on the
maximum load current and the value of the MOSFET’s
r_DS(ON).
R_CS
=
-^I-^M-----^A----^X-----^â‹---^r--^D-----^S---⁽---^O----^N----⁾
75 μ A
–
100
Ω
(EQ. 6)
Due to implemented current feedback, the modulator has a
single pole response with -1 slope at a frequency
determined by the load in Equation 7.
where: Ro -- is load resistance and Co -- is load capacitance.
F_PO
=
----------------¹----------------
2π ⋅ R_O ⋅ C_O
(EQ. 7)
For this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 5 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.;
F_Z
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
=
6kHz
(EQ. 8)
F_P
=
--------------¹----------------
2π ⋅ R₁ ⋅ C₂
=
600 k H z
(EQ. 9)
This region is also associated with phase ‘bump’ or
reduced phase shift. The amount of phase shift reduction
depends on how wide the region of flat gain is and has a
maximum value of 90°. To further simplify the converter
compensation, the modulator gain is kept independent of
the input voltage variation by providing feed-forward of V_IN
to the oscillator ramp.
C2
R2 ^C1
Converter
R1
EA
G_M = 18dB
Modulator
F_PO
Type 2 EA
G_EA = 14dB
F_Z
F_P
F_C
FIGURE 5. FEEDBACK LOOP COMPENSATION
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within 10kHz...50kHz range gives some
additional phase ‘boost’. Some phase boost can also be
achieved by connecting capacitor C_z in parallel with the
upper resistor R1 of the divider that sets the output voltage
value, as shown in Figure 2.
10
FN9069.3
April 12, 2007