X9241A_07 Datasheet, PDF (11/16 Pages) Intersil Corporation – Quad Digital Controlled Potentionmeters (XDCP™)

X9241A
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
100,000
100
UNIT
Data changes per bit per register
Years
Capacitance
SYMBOL
PARAMETER
C_I/O (Note 7)
C_IN (Note 7)
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3 and SCL)
TEST CONDITION
V_I/O = 0V
V_IN = 0V
TYP
19
12
UNIT
pF
pF
Power-up Timing
SYMBOL
PARAMETER
t_PUR (Note 8)
t_PUW (Note 8)
t_RV_CC
Power-up to initiation of read operation
Power-up to initiation of write operation
V_CC Power up ramp rate
MIN
(Note 11)
0.2
TYP
MAX
(Note 11)
1
5
50
UNIT
ms
ms
V/ms
Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V_CC, then the potentiometer pins. It is suggested that Vcc reach 90% of its
final value before power is applied to the potentiometer pins. The V_CC ramp rate specification should be met, and any glitches or
slope changes in the V_CC line should be held to <100mV if possible. Also, V_CC should not reverse polarity by more than 0.5V.
NOTES:
7. Limits should be considered typical and are not production tested.
8. Limits established by characterization and are not production tested.
9. Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
10. T_i value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse width that
is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device.
11. Parts are 100% tested at either +70°C or +85°C. Over temperature limits established by characterization and are not production tested.
AC Conditions of Test
Input pulse levels
Input rise and fall times
Input and output timing levels
Input pulse levels
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
V_CC x 0.1 to V_CC x 0.9
Symbol Table
WAVEFORM INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11
FN8164.6
August 31, 2007