ISL6336 Datasheet, PDF (10/31 Pages) Intersil Corporation – 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring

ISL6336, ISL6336A
Functional Pin Description
VCC - Supplies the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin directly to a +5V supply. Place a R/C filter
right next to this pin for noise decoupling. The resistor and
capacitor should be placed right next to the VCC pin to GND.
GND - Bias and reference ground for the IC. The exposed
metal pad on the bottom of the package of the ISL6336,
ISL6336A is GND.
EN_PWR - This pin is a threshold-sensitive enable input for
the controller. Connecting the 12V supply to EN_PWR
through an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the
ISL6336, ISL6336A is active depending on status of the
EN_VTT, the internal POR, and pending fault states. Driving
EN_PWR below 0.745V will clear all fault states and prime
the ISL6336, ISL6336A to soft-start when re-enabled.
EN_VTT - This pin is another threshold-sensitive enable
input for the controller. It’s typically connected to VTT output
of VTT voltage regulator in the computer mother board.
When EN_VTT is driven above 0.875V, the ISL6336,
ISL6336A is active depending on status of ENLL, the internal
POR, and pending fault states. Driving EN_VTT below
0.745V will clear all fault states and prime the ISL6336,
ISL6336A to soft-start when re-enabled.
FS - Use this pin to set up the desired switching frequency. A
resistor, placed from FS to GND or VCC will set the
switching frequency. The relationship between the value of
the resistor and the switching frequency is shown in
Equation 3. This pin is also used in combination with SS and
PSI# to determine phase dropping operation. See Table 1.
SS - Use this pin to set up the desired start-up oscillator
frequency. A resistor, placed from SS to GND or VCC will set
up the soft-start ramp rate. The relationship between the
value of the resistor and the soft-start ramp up time is
described in Equations 15 and 16. This pin is also used with
FS and PSI# pins to determine phase dropping operation.
See Table 1.
VID[7:0] - These are the inputs to the internal DAC that
generates the reference voltage for output regulation. The
pins have a minimum 30µA pull-up to about 1V after t_D3.
There is no internal pull-up before t_D3. Connect these pins to
open-drain outputs with external pull-up resistors or to active
pull-up outputs. The VID pins can be pulled as high as VCC
plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a single-
ended voltage referenced to local ground. VDIFF is the
amplifier’s output and the input to the regulation and protection
circuitry. Connect VSEN and RGND to the sense pins of the
remote load. VDIFF is connected to FB through a resistor.
FB and COMP - The inverting input and the output of the
error amplifier respectively. FB can be connected to VDIFF
through a resistor. A properly chosen resistor between
VDIFF and FB can set the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the
inductor DCR or the dedicated current sense resistor. COMP
is tied back to FB through an external R-C network to
compensate the regulator.
DAC and REF - The DAC pin is the output of the precision
internal DAC reference. The REF pin is the positive input of
the Error Amplifier. In typical applications, a 1kΩ, 1% resistor
is used between DAC and REF to generate a precision offset
voltage. This voltage is proportional to the offset current
determined by the offset resistor from OFS to ground or VCC.
A capacitor is used between REF and ground to smooth the
voltage transition during Dynamic VID™ operations.
PWM[6:1] - Pulse width modulation outputs. Connect these
pins to the PWM input pins of the Intersil driver IC. The
number of active channels is determined by the state of
PWM3, PWM4, PWM5, and PWM6. Tie PWM3 to VCC to
configure for 2-phase operation. Tie PWM4 to VCC to
configure for 3-phase operation. Tie PWM5 to VCC to
configure for 4-phase operation. Tie PWM6 to VCC to
configure for 5-phase operation. PWM firing order is
sequential from 1 to n with n being the number of active
phases.
ISEN[6:1]+, ISEN[6:1]- - The ISEN+ and ISEN- pins are
current sense inputs to individual differential amplifiers. The
sensed current is used for channel current balancing,
overcurrent protection, and droop regulation. Inactive
channels should have their respective current sense inputs
left open (for example, open ISEN6+ and ISEN6- for 5-phase
operation).
For DCR sensing, connect each ISEN- pin to the node
between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, R_ISEN.
The voltage across the sense capacitor is proportional to the
inductor current. Therefore, the sense current is proportional
to the inductor current, and scaled by the DCR of the
inductor and R_ISEN.
To match the time delay of the internal circuit, a capacitor is
needed between each ISEN+ pin and GND as described in
“Current Sensing” on page 14.
VR_RDY - VR_RDY indicates that the soft-start is completed
and the output voltage is within the regulated range around
VID setting. It is an open-drain logic output. When OCP or
OVP occurs, VR_RDY will be pulled to low. It will also be
pulled low if the output voltage is below the undervoltage
threshold.
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FN6504.1
May 28, 2009