316972-004 Datasheet, PDF (850/884 Pages) Intel Corporation – Intel I/O Controller Hub 9

Serial Peripheral Interface (SPI)
22.2.3
22.2.3.1
Flash Descriptor Region Section
The following section of the Flash Descriptor is used to identify the different Flash
Regions
Flash Regions:
• If a particular region is not using SPI Flash, the particular region should be disabled
by setting the Region Base to all 1's, and the Region Limit to all 0's (base is higher
than the limit)
• For each region except FLREG0, the Flash Controller must have a default Region
Base of FFFh and the Region Limit to 000h within the Flash Controller in case the
Number of Regions specifies that a region is not used.
FLREG0—Flash Region 0 Register (Flash Descriptor Registers)
Memory Address: FRBA + 000h
Size:
32 bits
Default Value: h
22.2.3.2
Bits
Description
31:29 Reserved
28:16 Region Limit. This specifies address bits 24:12 for the Region Limit.
15:13 Reserved
12:0 Region Base. This specifies address bits 24:12 for the Region Base.
FLREG1—Flash Region 1 (BIOS) Register (Flash Descriptor Registers)
Memory Address: FRBA + 004h
Size:
32 bits
Default Value: h
Bits
Description
31:29
28:16
15:13
12:0
Reserved
Region Limit. This specifies address bits 24:12 for the Region Limit.
Reserved
Region Base. This specifies address bits 24:12 for the Region Base.
NOTE: If the BIOS region is not used, the Region Base must be programmed to 1FFFh
and the Region Limit to 0000h to disable the region.
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Intel^® I/O Controller Hub 9 (ICH9) Family Datasheet