316972-004 Datasheet, PDF (256/884 Pages) Intel Corporation – Intel I/O Controller Hub 9

Functional Description
5.23.4.3.1
SPI Flash Unlocking Requirements for Management Engine
Flash devices must be globally unlocked (read, write and erase access on the ME
region) from power on by writing 00h to the flash’s status register to disable write
protection.
If the status register must be unprotected, it must use the enable write status register
command 50h or write enable 06h.
Opcode 01h (write to status register) must then be used to write a single byte of 00h
into the status register. This must unlock the entire part. If the SPI flash’s status
register has non-volatile bits that must be written to, bits [5:2] of the flash’s status
register must be all 0h to indicate that the flash is unlocked.
If there is no need to execute a write enable on the status register, then opcodes 06h
and 50h must be ignored.
After global unlock, BIOS has the ability to lock down small sections of the flash as long
as they do not involve the ME or GbE region.
5.23.4.4
Hardware Sequencing Requirements
The following table contains a list of commands and the associated opcodes that a SPI-
based serial flash device must support in order to be compatible with hardware
sequencing.
Table 5-59. Hardware Sequencing Commands and Opcode Requirements
Commands
Write to Status Register
Program Data
Read Data
Write Disable
Read Status
Write Enable
Fast Read
Enable Write to Status
Register
Erase
Full Chip Erase
JEDEC ID
Opcode
Notes
Writes a byte to SPI flash’s status register. Enable Write
01h
to Status Register command must be run prior to this
command.
02h
Single byte or 64 byte write as determined by flash part
capabilities and software.
03h
04h
05h
06h
0Bh
Outputs contents of SPI flash’s status register
50h or
06h
Program
mable
Enables a bit in the status register to allow an update to
the status register
256B, 4 Kbyte, 8 Kbyte or 64 Kbyte
C7h
9Fh
See Section .
5.23.4.4.1 JEDEC ID
Since each serial flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
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Intel^® I/O Controller Hub 9 (ICH9) Family Datasheet