316972-004 Datasheet, PDF (777/884 Pages) Intel Corporation – Intel I/O Controller Hub 9

PCI Express* Configuration Registers
20.1.13 SLT—Secondary Latency Timer
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Bh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base
Specification.
20.1.14 IOBL—I/O Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Ch–1Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:12
I/O Limit Address (IOLA) — R/W. I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8
I/O Limit Address Capability (IOLC) — R/O. Indicates that the bridge does not
support 32-bit I/O addressing.
7:4
I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0
I/O Base Address Capability (IOBC) — R/O. Indicates that the bridge does not
support 32-bit I/O addressing.
Intel^® I/O Controller Hub 9 (ICH9) Family Datasheet
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