82US15W Datasheet, PDF (7/22 Pages) Intel Corporation – Intel® System Controller Hub

Summary Tables of Changes
Errata
Stepping
No.
D1
D2
1
X
X
2
X
X
3
X
X
4
X
X
5
X
X
6
X
X
7
X
8
X
9
X
X
10
X
11
X
X
12
X
13
X
14
X
15
X
16
X
17
X
18
X
19
X
X
20
X
X
21
X
X
22
X
X
23
X
X
24
X
25
X
26
X
Status
Description
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Fixed
Fixed
No Fix
Fixed
No Fix
Fixed
Fixed
Plan Fix
Fixed
Fixed
Fixed
Fixed
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Audio Pops With High LPC Traffic
System Hang With PCIe Upstream Memory Write To FEE00000 With No Data
PCIe PLL May Not Power Down In L1 State
EHCI Controller—Unable To Mask Wake Events Per Port
PCIe Controller Fails To Go Into L1 State In Some Configurations
High Definition Audio Does Not Send Interrupts to the CPU using the MSI
Incorrect TPM Access
LPC Prefetch Outside of FWH Region
PATA Maximum Slew Rate Specification Violation
USB Client Drops Data Which Causes CRC Errors in Full-Speed Mode
System Hang During PCI Configuration Space Access
HD Audio Wall Clock Counter Alias Register
Reads From the HD Audio Wall Clock Counter Return the Same Value
SDIO CMD53 Timeout
SDIO Data Buffer Port 20h Read Error
Deadlock Causes Hang Condition Entering L1
Unrecognized USB Device
PCIE PCIHCT WHQL test hang
EHCI Controller Hang
PCIe Bridge Detects Correctable Errors During Tests
HDCTL and FD registers are reset during D3hot to D0 transition
High-speed USB 2.0 V_HSOH
PCIe Hang Due To Link Disconnect
PCI Express* unaligned memory read that crosses DWORD boundary causes data
corruption
USB Client High Speed termination delay to disconnect D+ pull-up resistor
USB audio device underrun/overrun while performing an isochronous transaction
Specification Changes
No.
SPECIFICATION CHANGES
1 There are no specification changes in this revision of the specification update.
Specification Clarifications
No.
SPECIFICATION CLARIFICATIONS
1 Correction to definition of SDIO bit PSTATE.CSS.
Specification Update
7