82US15W Datasheet, PDF (15/22 Pages) Intel Corporation – Intel® System Controller Hub

Errata
Status:
For the steppings affected, see the Summary Tables of Changes.
11.
System Hang During PCI Configuration Space Access
Problem:
When the HD audio controllers memory space enable (MSE) register is enabled and a
PCI configuration space cycle which is targeted to some other PCI device occurs that
also matches the HD audio controllers memory base address register, the HD audio
controller will claim this cycle. There are other conditions required to encounter this
erratum: a. HD au dio memory BAR (base address register) [31:24] must match the
configuration cycle number and b. HD audio memory BAR [23:19] must match
configuration cycle device number and c. HD audio memory BAR [18:16] must match
configuration cycle function number.
Implication: A system hang may occur as a result of the HD audio controller incorrect claim of the
PCI configuration cycle. This issue was found using a specific PCI bus test compliance
software. Typical systems do not have enough PCI busses (greater than 127) to
encounter this issue.
Workaround:None
Status:
For the steppings affected, see the Summary Tables of Changes.
12.
HD Audio Wall Clock Counter Alias Register
Problem:
Reads from the aliased wall clock counter register do not reflect the value of the wall
clock counter as stored in the non-aliased register, but only the last value read.
Implication: The Wall Clock counter registers are used to synchronize two or more HD audio
controllers. Systems based on the Intel SCH will only support a single audio controller
and no multi-controller synchronization is required.
Workaround:Do not use the aliased register.
Status:
For the steppings affected, see the Summary Tables of Changes.
13.
Reads From the HD Audio Wall Clock Counter Return the Same Value
Problem:
Consecutive reads of the wall clock counter will, under some circumstances, return the
same value.
Implication: The Wall Clock counter register is used to synchronize two or more HD audio controllers
by measuring the relative drift between their clocks. Systems based on Intel SCH will
only support a single audio controller and no m ulti-controller synchronization is
required. No end user impact is expected.
Workaround:None
Status:
For the steppings affected, see the Summary Tables of Changes.
14.
SDIO CMD53 Time-out
Problem:
During CMD53 PIO byte mode, the Intel SCH data time out counter times out after data
is transferred.
Implication: An SD counter reset occurs after the response completion and at the start of the data,
but if data starts (as allowed by the SDIO specification), prior to the response
completion the counter does not get reset and time out error occurs.
Workaround:Use block mode transfer.
Status:
For the steppings affected, see the Summary Tables of Changes.
15.
SDIO Data Buffer Port 20h Read Error
Problem:
An SDIO PIO mode data read from MMIO register offset 20h occasionally returns 0
(zero) instead of the data in the buffer.
Specification Update
15