82US15W Datasheet, PDF (17/22 Pages) Intel Corporation – Intel® System Controller Hub

Errata
20.
PCIe bridge detects correctable errors during tests
Problem:
During L0s and/or L1 entry or exit on the PCI Express root ports, the SCH may
acknowledge a co rrectable error, which violates the PCI Express spec, 1.0a. Th is is
reported thru the Correctable Error Detected bit (D28:F0/F1:Offset 4Ah:bit 0).
Implication: No system functionality issues observed. However, correctable error logging may not
accurately report the number of errors. Note: No known end-user SW uses this
logging capability.
Workaround:None.
Status:
For the steppings affected, see the Summary Tables of Changes.
21.
HDCTL and FD registers are reset during D3hot to D0 transition
Problem:
During D3hot to D0 transition in the High Definition Audio Controller, the HDCTL and FD
registers are reset. These registers are not exposed to the Windows HD Audio driver
and thus cannot be restored by Windows after a D3hot to D0 transition.
Implication: HDCTL.LVME is cleared. If the controller is operating in low voltage mode (i.e. 1.5V
instead of 3.3V), the HDA BITCLK does not re-activate. The HDA Device will not
operate until BIOS has reset the bit upon system awaken or restart.
FS.MD is cleared, thus enabling MSI. No further implication, as HDA MSI is inoperative
per Erratum 50.
Workaround:BIOS can add ACPI methods (_PS0 specifically) for the HDA Controller to program the
following bits during the D3 to D0 transition:
• Bus 0, Device 27, Function 0, offset 40h. Bit 0 should be “1” to enable Low Voltage
(1.5V) mode (needed for 1.5V I/O systems)
Status:
• Bus 0, Device 27, Function 0, offset FCh. Bit 1 should be “1” to disable MSI
capability
For the steppings affected, see the Summary Tables of Changes.
22.
High-speed USB 2.0 V_HSOH
Problem: High-speed USB 2.0 V_HSOH may not meet the USB 2.0 specification.
• The maximum expected V_HSOH is 460 mV.
Implication: None known.
Workaround:None.
Status:
For the steppings affected, see the Summary Tables of Changes.
23.
PCIe Hang Due To Link Disconnect
Problem:
When a PCIe link is disconnected and then reconnected in such a way that a link reset
is required, internal queue logic which manages transactions on the link may become
corrupted. Examples of link disconnect and reconnect include removing and reinserting
a PCIe Express Card, or a PCIe device disabling and enabling the PCIe link for power
management purposes.
Implication: This corruption will subsequently result in system retry failures that will lead to a
system hang at an undetermined time.
Workaround:PCIe Express Card devices should be plugged in only when the system is powered off
or in a suspend state. All attached PCIe devices should keep the PCIe link connected at
all times.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
17