82573 Datasheet, PDF (7/39 Pages) Intel Corporation – GbE Controllers

Datasheet—82573
1.0
Note:
Introduction
Unless specifically noted, 82573 refers to the Intel® 82573E, 82573V and 82573L GbE
controllers.
82573 GbE controllers are single, compact components with integrated Gigabit
Ethernet Media Access Control (MAC) and Physical Layer (PHY) functions. These
devices use PCIe* architecture (Revision 1.0a). For desktop, workstation, and value
server network designs with critical space constraints, the 82573 enables a GbE
implementation in a very small area.
The 82573 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab, respectively).
In addition to managing MAC and PHY Ethernet layer functions, the 82573 manages
PCIe* packet traffic across its transaction, link, and physical and logical layers.
The 82573E contains a dedicated microcontroller for manageability with an on-board
Intel^® Active Management Technology (Intel^® AMT) enabling network. This enables
manageability implementations required by information technology personnel for out-
of-band management, remote troubleshooting and recovery, asset management, and
non-volatile storage. Intel^® AMT is the first step towards a complete Intel^® Cross-
Platform Manageability Program (Intel® CPMP), which is a business and technology
initiative to deliver consistent management capabilities, protocols, and interfaces
across all Intel platforms.
The 82573E and 82573V GbE controllers have an integrated System Management Bus
(SMBus) port enabling industry standards, such as the Alert Standard Forum (ASF) 2.0.
With SMBus, management packets can be routed to or from a management processor.
In addition, integrated ASF 2.0 circuitry provides alerting and capabilities with
standardized interfaces.
The 82573 with PCIe* architecture is designed for high performance and low memory
latency. The device is optimized to connect to a system I/O Control Hub (ICH7) using
one PCIe* lane. Alternatively, the 82573 is able to connect to a Memory Control Hub
(MCH) device with a PCIe* interface.
Wide internal data paths eliminate performance bottlenecks by efficiently handling
large address and data words. The 82573 efficiently handles packets with minimum
latency by combining a parallel and pipelined logic architecture optimized for GbE and
independent transmit and receive queues. The 82573 also includes advanced interrupt
handling features and uses efficient ring buffer descriptor data structures, with up to 64
packet descriptors per queue cached on chip. A 32-KB on-chip packet buffer maintains
superior performance. In addition, using hardware acceleration, the 82573 offloads
tasks from the host (for example, TCP/UDP/IP checksum calculations and TCP
segmentation).
The 82573L features low power management. During the L1 and L2 link states, the
82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe*
reference clock can be gated.
The 82573 is packaged in a 15 mm X 15 mm, 196-Ball Grid Array (BGA).
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