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82573 Datasheet, PDF (1/39 Pages) Intel Corporation – GbE Controllers | |||
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82573 Family of GbE Controllers
Datasheet
Product Features
 PCIe*
â x1 PCIe* interface on ICH7 or MCH devices
â Peak bandwidth: 2 Gb/s per direction
â Power management
â High bandwidth density per pin
 MAC
â Optimized transmit and receive queues
â IEEE 802.3x compliant flow control with
software controlled pause times and threshold
values
â Caches up to 64 packet descriptors per queue
â Programmable host memory receive buffers
(256 bytes to 16 KB) and cache line size (16
bytes to 256 bytes)
â 32 KB configurable transmit and receive FIFO
buffer
â Mechanism available for reducing interrupts
generated by transmit and receive operation
â Descriptor ring management hardware for
transmit and receive
â Optimized descriptor fetching and write-back
mechanisms
â Wide, pipelined internal data path architecture
 PHY
â Integrated PHY for 10/100/1000 Mb/s full and
half duplex operation
â IEEE 802.3ab auto negotiation support
â IEEE 802.3ab PHY compliance and
compatibility
â DSP architecture implements digital
adaptive equalization, echo cancellation,
and cross-talk cancellation
 Host Offloading
â Transmit and receive IP, TCP and UDP
checksum off-loading capabilities
â Transmit TCP segmentation, IPv6 offloading,
and advanced packet filtering
â IEEE 802.1q VLAN support with VLAN tag
insertion, stripping and packet filtering for up
to 4096 VLAN tags
â Descriptor ring management hardware for
transmit and receive
 Manageability
â Intel® Active Management Technology (Intel®
AMT) support (82573E only)
â Alerting Standards Format 2.0 and advanced
pass through support (82573E/V only)
â Boot ROM Preboot eXecution Environment
(PXE) Flash interface support
â Compliance with PCI Power Management 1.1
and Advanced Configuration and Power
Interface (ACPI) 2.0 register set compliant
â Wake on LAN support
 Additional
â Three activity and link indication outputs that
directly drive LEDs
â Programmable LEDs
â Internal PLL for clock generation that can use
a 25 MHz crystal
â Power saving feature for the 82573L. During
the L1 and L2 link states, the 82573L asserts
the Clock Request signal (CLKREQ#) to
indicate that its PCIe* reference clock can be
gated
â On-chip power control circuitry
â Loopback capabilities
â JTAG (IEEE 1149.1) Test Access Port (TAP)
built in silicon
 Technology
â Lead-free 196-pin Thin and Fine Pitch Ball Grid
Array (TF-BGA) package
â Operating temperature: 0° C to 70° C (with
external regulators)
â Operating temperature: 0° to 55° C (with on-
die 2.5V regulator)
â Storage temperature -40° C to 125° C
Order Number: 315514-002
Revision 2.5
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