QGE7520MC-SL8EE Datasheet, PDF (45/282 Pages) Intel Corporation – Intel® E7520 Memory Controller Hub (MCH)

Register Descriptions
3.5.5
3.5.6
3.5.7
RID – Revision Identification (D0:F0)
Address Offset:
Access:
Size:
Default:
08h
RO
8 Bit
09h
This register contains the revision number of MCH Device 0.
Bit Field
7:0
Default &
Access
Description
09h
R/WO
Revision Identification Number (RID). This value indicates the revision
identification number for MCH Device 0.
09h = C1 stepping.
0Ah = C2 stepping.
0Ch = C4 stepping.
SUBC – Sub-Class Code (D0:F0)
Address Offset:
Access:
Size:
Default:
0Ah
RO
8 Bits
00h
Bit Field
7:0
Default &
Access
Description
00h
Sub-Class Code (SUBC). This value indicates the Sub Class Code into which
RO
MCH Device 0 falls.
00h = Host Bridge.
BCC – Base Class Code (D0:F0)
Address Offset:
Access:
Size:
Default:
0Bh
RO
8 Bits
06h
Bit Field
7:0
Default &
Access
Description
06h
Base Class Code (BASEC). This value indicates the Base Class Code for MCH
RO
Device 0.
06h = Bridge device.
Intel^® E7520 Memory Controller Hub (MCH) Datasheet
45