QGE7520MC-SL8EE Datasheet, PDF (17/282 Pages) Intel Corporation – Intel® E7520 Memory Controller Hub (MCH)

1 Introduction
This document details the system architecture supported by the Intel^® E7520 MCH, its external
interfaces, and other features visible to hardware and software designers implementing a E7520
platform. Included in this specification are descriptions and pin listings for all external electrical
interfaces, descriptions of internal registers, and descriptions of the MCH.
1.1
Terminology
Term
Agent
Asserted
Asynchronous
Buffer
Cache Line
CAM
Cfg
Coherent
Command
Completion
Core
CRC
Deasserted
DED
Deferred
Transaction
Delayed
Transaction
DMA
Downstream
Description
A logical device connected to a bus or shared interconnect that can either initiate and/or
be the target of accesses.
Signal is set to a level that represents logical true.
1. An event that causes a change in state with no relationship to a clock signal.
2. When applied to transactions or a stream of transactions, a classification for those
that do not require service within a fixed time interval.
1. A random access memory structure.
2. The term I/O buffer is also used to describe a low level input receiver and output
driver combination.
The unit of memory that is copied to and individually tracked in a cache. Specifically,
64 bytes of data or instructions aligned on a 64-byte physical address boundary.
Content Addressable Memory
Used as a qualifier for transactions that target PCI configuration address space.
Transactions that ensure that the processor's view of memory through the cache is
consistent with that obtained through the I/O subsystem.
The distinct phases, cycles, or packets that make up a transaction. Requests and
Completions are referred to generically as Commands.
A packet, phase, or cycle used to terminate a Transaction on an interface, or within a
component. A Completion will always refer to a preceding Request and may or may not
include data and/or other information.
The internal, base logic of a component.
Cyclic Redundancy Check. A number derived from, and stored or transmitted with, a
block of data in order to detect corruption. By recalculating the CRC and comparing it to
the value originally transmitted, the receiver can detect some types of transmission
errors.
Signal is set to a level that represents logical false.
Double-bit Error Detect
A processor bus Split Transaction. The requesting agent receives a Deferred Response
which allows other transactions to occur on the bus. Later, the response agent
completes the original request with a separate Deferred Reply transaction.
A transaction where the target retries an initial request, but unknown to the initiator,
forwards or services the request on behalf of the initiator and stores the completion or
the result of the request. The original initiator subsequently re-issues the request and
receives the stored completion
Direct Memory Access. Method of accessing memory on a system without interrupting
the processors on that system
Describes commands or data flowing away from the processor-memory complex and
toward I/O. The terms Upstream and Downstream are never used to describe
transactions as a whole. For example, downstream data may be the result of an
Outbound Write, or an Inbound Read. The Completion to an Inbound Read travels
Downstream.
Intel^® E7520 Memory Controller Hub (MCH) Datasheet
17