QGE7520MC-SL8EE Datasheet, PDF (244/282 Pages) Intel Corporation – Intel® E7520 Memory Controller Hub (MCH)

Functional Description
acknowledged, the power management device may be notified that it is cleared to modify the
collective power state of the PCI Express hierarchy. These message packets have posted semantics
on the interface, thus the turn-off will “push” all prior packets to their endpoints, and the
acknowledge will “push” any pending inbound traffic all the way to the root. This prevents
“trapping” transactions or PME messages somewhere in the hierarchy at the time power is
dropped, ultimately causing them to be lost.
In a pure PCI Express design, the PME_TURN_OFF packet would originate directly at the power
manager, or perhaps at the ICH equivalent device providing connection between the power
manager and the remainder of the core logic. Neither the power manager nor the ICH is aware of
the PCI Express messaging mechanism, thus the MCH provides device-specific control and status
bits for use by its ACPI BIOS. The sequence of events to place an PCI Express device in an
unpowered state within the platform is as follows:
• PCI-PM or ACPI compliant O/S software is called to place the system into a low power sleep
state (S3, S4 or S5), prepares for suspension, and calls ACPI BIOS to carry out the platform
power transition.
• The BIOS then communicates to the root complex that all PCI Express devices should prepare
for power-off. This is accomplished through the device-specific configuration space of the
internal virtual PCI-to-PCI bridges with subordinate PCI Express hierarchies. BIOS must
configure each active root port to power down. When the configuration write is received to set
the “PM Turn Off” bit, the associated root port will transmit a PM_Turn_Off message
downstream. At this point, any traffic in-flight continues to be handled normally by the MCH
– routed outbound, and completed inbound.
• The target PCI Express device ceases generation of new transactions inbound, waits for all
pending transactions to complete, and prepares to lose power and clocking. If the target device
has a subordinate hierarchy of its own, it will propagate the PM_Turn_Off message
downstream and wait for acknowledges from all subordinate ports. Once ready to be brought
off-line, the target device issues a PM_TO_Ack TLP cycle in acknowledgement back to the
root. Note that the link is still communicative at this point, with both power and clock
available.
• After issuing the PM_TO_Ack cycle, the downstream device then issues a PM_Enter_L23
DLLP continuously upstream until it receives an acknowledge. In response to the
PM_TO_Ack, the root port will set its “Turn Off Back” status bit. In response to the
PM_Enter_L23 DLLP, the root will transition its downstream link to the electrical idle state.
• ACPI BIOS, which has been spinning waiting for all of the “Turn Off Ack” status bits to
assert, now clears all the command and status bits associated with the PME_TURN_OFF. The
routine then informs the power manager to go ahead with the change to the system power
state.
• The power manager drops power and clocking to the target device(s), and all associated links
automatically transition to either the L2 or L3 uncommunicative power states. The links will
enter L2 if Vaux is supplied by the platform, otherwise they will enter L3. The platform will
remain in the low power state until a wake event is signaled.
In a fully PCI Express aware core logic implementation, the ACPI BIOS would not need to act as
the interlock between the MCH and the power manager, as all that functionality would be handled
in hardware via direct messaging. The combination of the added registers and the added software
support compensate for the schizophrenic nature.
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Intel^® E7520 Memory Controller Hub (MCH) Datasheet