LUPXA255A0C200 Datasheet, PDF (38/40 Pages) Intel Corporation – Electrical, Mechanical, and Thermal Specification

Electrical Specifications
Figure 8. SSP AC Timing Definitions
SCLK_C
SFRM_C
TXD_C
RXD_C
Tsfmv
Tsfmv
Trxds
Trxdh
A4774-01
Table 24. SSP AC Timing Specifications
Symbol
Description
Min
Tsfmv
SCLK_C rise to SFRM_C driven valid
Trxds
RXD_C valid to SCLK_C fall (input setup)
11
SCLK_C fall to RXD_C invalid (input
Trxdh
hold)
0
Tsfmv
SCLK_C rise to TXD_C valid
Max
21
22
Units
ns
ns
ns
ns
Notes
4.9.3
Boundary Scan Test Signal Timings
Table 25, “Boundary Scan Test Signal Timing” shows the boundary scan test signal timing.
Table 25. Boundary Scan Test Signal Timing (Sheet 1 of 2)
Symbol
Parameter
TBSF TCK frequency
TBSCH TCK high time
TBSCL TCK low time
TBSCR TCK rise time
TBSCF TCK fall time
TBSIS1 Input setup to TCK TDI, TMS
TBSIH1 Input hold from TCK TDI, TMS
TBSIS2 Input setup to TCK nTRST
TBSIH2 Input hold from TCK nTRST
TBSOV1 TDO valid delay
TOF1 TDO float delay
TOV12 All outputs (non-test) valid delay
Min Max Units
Notes
0.0 33.33 MHz
15.0
ns Measured at 1.5 V
15.0
ns Measured at 1.5 V
5.0 ns 0.8 V to 2.0 V
5.0 ns 2.0 V to 0.8 V
4.0
ns
6.0
ns
25.0
3.0
1.5 6.9
1.1 5.4
1.5 6.9
ns
ns
ns Relative to falling edge of TCK
ns Relative to falling edge of TCK
ns Relative to falling edge of TCK
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Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification